AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

ID 683731
Date 1/30/2018
Document Table of Contents Deterministic Latency Measurement Module

The link latency of the design is measured from the TX core is ready to accept data (the rise of) until the data to the RX transport layer is valid. The RBD count varies from 0 to ((FxK/4)-1), which is 0 to 7. You may observe the RBD count=0 or 7 in this FMC external loopback setup. In this scenario, deterministic latency is not guaranteed because the RBD elastic buffer can be released either at the current LMFC boundary when RBD count=0 or one local multi-frame period later at the next LMFC boundary when RBD count=7. During multiple power cycles of the board, you may observe the link latency of 26 or 34 link clock cycles when RBD count is 0 or 7. Due to this, the lane de-skew error could happen during link initialization. To fix the deterministic latency issue, the csr_rbd_offset is programmed to 5 to force the release of RBD elastic buffer 5 LMFC counts before the next LMFC boundary. By setting RBD offset value equal to 5, the counter consistently shows link latency of 29 link clock cycles from one power cycle to another power cycle.

Figure 14. Early RBD Release Opportunity for Latest Arrival Lane Across Two Multi-frames

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