AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

ID 683731
Date 1/30/2018
Document Table of Contents PLL Reconfiguration Controller

The PLL reconfiguration controller (altera_pll_reconfig) facilitates dynamic real-time reconfiguration of the core PLL. You can use this IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without reconfiguring the entire FPGA. The PLL reconfiguration controller connects to the Nios® II processor via the Avalon® -MM interconnect. The Nios® II processor sends dynamic reconfiguration instructions to the controller during a dynamic data rate reconfiguration operation. This is an optional component because the design only showcases a static data rate operation.