1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
220.127.116.11.4. PLL Reconfiguration Controller
The PLL reconfiguration controller (altera_pll_reconfig) facilitates dynamic real-time reconfiguration of the core PLL. You can use this IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without reconfiguring the entire FPGA. The PLL reconfiguration controller connects to the Nios® II processor via the Avalon® -MM interconnect. The Nios® II processor sends dynamic reconfiguration instructions to the controller during a dynamic data rate reconfiguration operation. This is an optional component because the design only showcases a static data rate operation.
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