AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

ID 683731
Date 1/30/2018
Public
Document Table of Contents

1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

Date Version Changes
January 2018 2018.01.30 Renamed the document as AN 814: Intel Arria 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design.
December 2017 2017.12.18
  • Renamed the document as AN 814: Intel Arria 10 Two x8-Lanes JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design using Nios II Processor.
  • Added a note to clarify that the IOPLL input reference clock is sourcing from device clock through global clock network in the Clocking Scheme topic.
  • Updated for latest branding standards.
  • Made editorial updates throughout the document.
June 2017 2017.06.15 Initial release.

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