AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

ID 683731
Date 1/30/2018
Document Table of Contents Nios® II Subsystem in Platform Designer

The Nios® II subsystem Platform Designer project, nios_subsystem.qsys, instantiates the following peripherals:

  • Nios® II processor
  • On-chip memory (altera_avalon_onchip_memory2)—provides both instruction and data memory space
  • Timer—provides a general timer function for the software
  • JTAG UART—serves as the main communications portal between the user and the Nios® II processor via the terminal console in Nios® II SBT for Eclipse tool
  • Avalon® -MM bridges—two Avalon® -MM bridge modules; one to interface to the JESD204B subsystem and the other interface to the Platform Designer components (core PLL reconfiguration controller and SPI master module)
  • PIO—provides general input/output (I/O) access from the Nios® II processor to the HDL components in the FPGA via two sets of 32-bit registers:
    • io_status—status registers input from the HDL components to the Nios® II processor
    • io_control—control registers output from the Nios® II processor to the HDL components
Table 10.   Signal Connectivity for io_status Registers
Bit Signal
0 Core PLL locked
1 TX transceiver ready (Link 0/Instance 0)
2 RX transceiver ready (Link 0/Instance 0)
3 Test pattern checker data error (Link 0/Instance 0)
4–31 TX transceiver ready, RX transceiver ready, and test pattern checker data error signals for subsequent JESD204B IP cores (Link 1-9/ Instance 1-9), if present.
Table 11.   Signal Connectivity for io_control Registers
Bit Signal
0 RX serial loopback enable for two JESD204B IP cores in this design
1 Reserved
2 Reserved
3 Reserved
4–30 Reserved
31 Sysref

You can access the address map of the submodules in the Nios® II subsystem by clicking on the Address Map tab in the Platform Designer window.