AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

Download PDF
ID 683731
Date 1/30/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.3.1.1. Platform Designer Top System Component

The Platform Designer top system instantiates both the JESD204B IP core data path and the Nios® II subsystem control path.

Figure 8.  Platform Designer System Top Level Block Diagram

The top level Platform Designer system, jesd204b_ed_qsys.qsys, instantiates the following modules:

  • JESD204B subsystem
  • Nios® II subsystem
  • Core PLL
  • PLL reconfiguration controller
  • IRQ bridge

The main data flows through the JESD204B subsystem. The frame data from pattern generator is forwarded to the assembler (TX transport layer). The assembler maps the frame data to non-scrambled octet stream data to the transceiver lane. Each lane has 32-bits of parallel data in Avalon-ST protocol. For each L=8 IP core, the total parallel data bus width is 256 bits. The TX link layer (JESD204B IP core) receives this octet stream data from the assembler, performs scrambling (if enabled) and inserts alignment characters before forwarding the octet stream data to the physical layer. The physical layer (PHY) is part of the JESD204B IP core. The 8b/10 encoded data from the physical layer is transmitted from the high speed serial link transmitter into the FMC loopback card. The FMC loopback card provides a passive pass through of the serial data from the transmitter to the receiver. At the physical layer of the receiver, the 8b/10b decoding is performed and the running disparity and not-in-table errors are monitored. The RX link layer performs lane/frame alignment, octet reconstruction and de-scrambles (if enabled) the data. The RX link layer outputs 8 lanes of 32-bit parallel data/lane in Avalon® -ST protocol to the de-assembler (RX transport layer). The de-assembler maps the octet data stream to the frame data. Finally, the pattern checkers verify the data integrity of the frame data.

The Nios® II processor in the Nios® II subsystem is the Avalon® -MM master of the control path. The Avalon® -MM slaves such as the JESD204B IP cores and peripherals are connected to the Nios® II processor through the Avalon® -MM Pipeline Bridges. The core PLL generates the link clock and frame clock for the system. The mgmt_clk is directly sourced from external oscillator. To view the top level Platform Designer system in Platform Designer, perform the following steps:

  1. Launch the Intel® Quartus® Prime software.
  2. On the File menu, click Open.
  3. Browse and select the jesd204b_ed_qsys.qsys file located in the project directory.
  4. Click Open to view the Platform Designer system.

You can access the address mapping of the submodules in the top level Platform Designer project by clicking on the Address Map tab in the Platform Designer window.

Figure 9. Top-Level Address Map View in Platform Designer

Section Content
JESD204B Subsystem
Nios II Subsystem in Platform Designer
Core PLL
PLL Reconfiguration Controller
SPI Master

Level Two Title