AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

ID 683731
Date 1/30/2018
Document Table of Contents Core PLL

The core PLL is an Intel® Arria® 10 I/O PLL (altera_iopll) module that generates the clocks for the FPGA core fabric.

For the frame clock, when F=1 and F=2, the resulting frame clock frequency can easily exceed the capability of the core. Thus, the top-level RTL file ( defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F=1) and F2_FRAMECLK_DIV (for cases with F=2). This factor enables the transport layer and test pattern generator/checker to operate at a divided factor of required frame clock rate by widening the transport layer Avalon® -ST interface data width accordingly. For this reference design, the F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2. For example, the actual frame clock and link clock required for a serial data rate of 6.0 Gbps and F=1 in this design is calculated as below:

Table 12.  Clocks
Clock Formula Description
Link Clock (from output C0) Serial data rate/40 The link clock clocks the link layer JESD204B IP cores, link interface of transport layer, multi-stage pipeline for SYSREF, deterministic latency measurement module.
Frame Clock (from output C1) Serial data rate/(10 × F) The frame clock clocks the transport layer, test pattern generators and checkers.

Frame clock = 6000/(10x1)/F1_FRAMECLK_DIV= 600/4= 150Mhz

Link clock = 6000/40= 150Mhz