1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2.5. Reconstructing Design and Running in Hardware
Perform the following steps to reconstruct the design and run it in hardware:
- Regenerating files and configuring the FPGA.
- Rebuilding Nios® II software and initializing the JESD204B link.
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