AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

ID 683731
Date 1/30/2018
Document Table of Contents

1.2.5. Reconstructing Design and Running in Hardware

Perform the following steps to reconstruct the design and run it in hardware:

  1. Regenerating files and configuring the FPGA.
  2. Rebuilding Nios® II software and initializing the JESD204B link.