AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

ID 683731
Date 1/30/2018
Document Table of Contents

1.2.2. Running the Reference Design

Perform the following steps to run the reference design:

  1. Configure the FPGA
  2. Execute the software C code and initialize the JESD204B link