AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design
ID
683731
Date
1/30/2018
Public
Visible to Intel only — GUID: qbx1494916801878
Ixiasoft
1.3. Reference Design Functional Description
The design runs on the Intel® Arria® 10 GX FPGA Development Kit.
Figure 7. System level Block Diagram
The reference design consists of the following key modules:
- Top Level HDL
- Platform Designer Top Level System
- JESD204B Subsystem
- Reset Sequencer
- JESD204B IP cores
- Transceiver PHY Reset Controller
- fPLL
- Avalon® -MM Pipeline Bridge
- Nios® Subsystem
- Nios® II Processor
- On-chip Memory
- JTAG UART
- Timer
- PIO
- Avalon® -MM Bridge
- Core PLL and core PLL reconfiguration controller
- SPI Master
- JESD204B Subsystem
- Transport layer
- Assembler (TX data path)
- Deassembler (RX data path)
- Test Pattern Generator and Checker
- Deterministic Latency Measurement Module
- Frequency Checker