AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

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ID 683731
Date 1/30/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.3.1. Top Level HDL

The Platform Designer top system, transport layer, test pattern generator and checker, deterministic latency measurement and frequency checker modules are instantiated in the top-level HDL file called jesd204b_ed.sv. The top-level HDL file located at the <project directory>/ directory includes the project parameters that define the configuration of the reference design.

Table 7.  Top level HDL File Parameters
Parameter Description
LINK Number of JESD204B link. One link represents one JESD204B instance. A link composed of multiple lanes. Set to match the configuration in JESD204B IP core parameter editor.
SUBSYSTEM

Number of JESD204B subsystem in Platform Designer top level system. A JESD204B subsystem may contain multiple links that requires for multi-devices synchronization.

L Number of JESD204B lanes per converter device. Set to match the configuration in JESD204B IP core parameter editor.
M Number of JESD204B converters per device. Set to match the configuration in JESD204B IP core parameter editor.
F Number of JESD204B octets per frame. Set to match the configuration in JESD204B IP core parameter editor.
N Number of JESD204B conversion bits per converter device. Set to match the configuration in JESD204B IP core parameter editor.
N_PRIME Number of JESD204B transmitted bits per sample. Set to match the configuration in JESD204B IP core parameter editor.
S Number of JESD204B transmitted samples per converter device per frame. Set to match the configuration in JESD204B IP core parameter editor.
CS Number of JESD204B control bits per conversion sample. Set to match the configuration in JESD204B IP core parameter editor.
F1_FRAMECLK_DIV Divider ratio for frame_clk when F=1. Refer to the JESD204B IP Core Design Example User Guide for more details.
F2_FRAMECLK_DIV Divider ratio for frame_clk when F=2. Refer to the JESD204B IP Core Design Example User Guide for more details.
POLYNOMIAL_LENGTH Defines the polynomial length for the PRBS pattern generator and checker. Refer to the JESD204B IP Core Design Example User Guide for more details.
FEEDBACK_TAP Defines the feedback tap for the PRBS pattern generator and checker. Refer to the JESD204B IP Core Design Example User Guide for more details.

Section Content
Platform Designer Top System Component
Transport Layer
Test Pattern Generator
Test Pattern Checker
Deterministic Latency Measurement Module
Frequency Checker

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