AN 814: Intel Arria 10 Two x8-Lane JESD204B (Duplex) IP Cores Multi-Device Synchronization Reference Design

Download PDF
ID 683731
Date 1/30/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design x
1.1. Hardware and Software Requirements 1.2. Reference Design Walkthrough 1.3. Reference Design Functional Description 1.4. Document Revision History for AN 814: Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design
1.2. Reference Design Walkthrough x
1.2.1. Hardware Setup 1.2.2. Running the Reference Design 1.2.3. Software Parameters 1.2.4. Software Functions Description 1.2.5. Reconstructing Design and Running in Hardware 1.2.6. Viewing the Results
1.2.2. Running the Reference Design x
1.2.2.1. Configuring the FPGA 1.2.2.2. Executing the Software C Code and Initializing the JESD204B Link
1.2.4. Software Functions Description x
1.2.4.1. Functions in main.c Source File 1.2.4.2. Custom Peripheral Access Macros in macros.c Source File
1.2.5. Reconstructing Design and Running in Hardware x
1.2.5.1. Regenerating Files, Recompiling Design and Configuring the FPGA 1.2.5.2. Rebuilding Software and Initializing the JESD204B Link
1.3. Reference Design Functional Description x
1.3.1. Top Level HDL 1.3.2. Clocking Scheme 1.3.3. FPGA Pin Assignments
1.3.1. Top Level HDL x
1.3.1.1. Platform Designer Top System Component 1.3.1.2. Transport Layer 1.3.1.3. Test Pattern Generator 1.3.1.4. Test Pattern Checker 1.3.1.5. Deterministic Latency Measurement Module 1.3.1.6. Frequency Checker
1.3.1.1. Platform Designer Top System Component x
1.3.1.1.1. JESD204B Subsystem 1.3.1.1.2. Nios® II Subsystem in Platform Designer 1.3.1.1.3. Core PLL 1.3.1.1.4. PLL Reconfiguration Controller 1.3.1.1.5. SPI Master
1.3.1.1.2. Nios® II Subsystem in Platform Designer x
1.3.1.1.2.1. Nios® II Processor 1.3.1.1.2.2. Nios® II Subsystem Address Map
1. Intel® Arria® 10 Two x8-Lane JESD204B IP Cores (Duplex) Multi-Device Synchronization Reference Design

1.3.1.3. Test Pattern Generator

The test pattern generator has three patterns options; PRBS, alternate checkerboard, or RAMP wave. The test pattern is sent to the transport layer when test mode is selected. By default, the PRBS pattern test mode is selected.
Level Two Title