PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/10/2023

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Document Table of Contents
Give Feedback Output Path

The simplified output path consists of pipeline registers, TX FIFO, shift register, and phase shift blocks. The following figure shows strobe and data coming from the core together with relative enable signals go through pipeline stages before TX FIFO.
Figure 3. Simplified Output PathThis figure shows the simplified output path for the PHY Lite for Parallel Interfaces IP.
Table 4.  Components in Simplified Output Path
Component Description
Pipeline Registers Represent pipeline stages in the output path.
TX FIFO Stores the data to be transmitted out.
Shift Register Delays the enable signal at the read side of the TX FIFO at VCO cycle increment.
Phase Shift Delays TX data and strobe at 1/128 of a VCO cycle increments.

There are two types of delays in the output path, namely inherent latency and output delay, TxDqDelay. The inherent latency is a static delay and is captured in the pipeline stages from the assertion of output enable in the core until the data goes in TX FIFO. The GUI parameter Additional Write Latency is added to the inherent latency.

The TxDqDelay is a dynamic delay and can be reconfigured in the control registers. It is an 11-bit wide register with details described in the following table. It is made up of two parts; the integer part in terms of VCO clock cycles, and the phase shift measured in 1/128 of a VCO clock period. The integer portion of the delay is accomplished using a shift register to delay the enable signal that goes to the read side of the TX FIFO.

Table 5.  Output Path Reconfigurable Delays DescriptionThis table describes the reconfigurable output path delay.
Feature Description Min Max


Integer number of VCO clock cycles 0 15


Additional phase shift measured in 1/128 of VCO clock period 0 127
Figure 4. Output OperationThis figure shows the output operation for the PHY Lite for Parallel Interfaces IP.

The preceding figure shows an example of TX data transfer in QR DDR. The data_from_core for each pin is 8 bits wide. To enable one extra preamble cycle before the data starts, strobe_out_en should first transition from 0 to 8 one core clock cycle before the data output enable as shown in the figure. Setting Output strobe phase to 90 degrees causes PHY Lite to send the data center aligned.