PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

5.3.2.5. Termination Signals

Table 104.  Termination SignalsThe termination signals are signals that are available when you enable the Expose termination ports parameter.
Signal Name Direction Width Description
group_seriesterminationcontrol Input

16

Connect this signal to the series termination control signal of the OCT Intel® FPGA IP to receive series termination code to calibrate Rs.
group_parallelterminationcontrol Input

16

Connect this signal to the parallel termination control signal of the OCT Intel® FPGA IP to receive parallel termination code to calibrate Rt.