Visible to Intel only — GUID: hap1599794014461
Ixiasoft
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.2.1. Intel® Agilex™ 7 for F-Series and I-Series I/O Sub-bank Interconnects
3.2.2. Intel® Agilex™ 7 for F-Series and I-Series Input DQS/Strobe Tree
3.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ 7 for F-Series and I-Series FPGA IP Top Level Interfaces
3.2.4. Dynamic Reconfiguration
3.2.5. I/O Timing
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: hap1599794014461
Ixiasoft
4.4.1. Input Buffer Reference Voltage (VREF)
The POD I/O standard allows configurable VREF. By default, the externally provided VREF is used and using an internal VREF requires the following .qsf assignments:
set_instance_assignment -name VREF_MODE <mode> -to <pin_name>
Note: The VREF settings are at the lane level, so all pins using a lane must have the same VREF settings (including GPIOs).
VREF Mode | Description |
---|---|
EXTERNAL | Use the external VREF. This is the default. |
CALIBRATED | Use internal VREF generated using VREF codes from the Avalon memory-mapped reconfiguration bus. |
VCCIO_45 | Use internal VREF generated using static VREF code. VREF is 45% of VCCIO |
VCCIO_50 | Use internal VREF generated using static VREF code. VREF is 50% of VCCIO |
VCCIO_55 | Use internal VREF generated using static VREF code. VREF is 55% of VCCIO |
VCCIO_65 | Use internal VREF generated using static VREF code. VREF is 65% of VCCIO |
VCCIO_70 | Use internal VREF generated using static VREF code. VREF is 70% of VCCIO |
VCCIO_75 | Use internal VREF generated using static VREF code. VREF is 75% of VCCIO |
Figure 57. VREF
Note: You must select the VREF range for your design using analog simulation.