Visible to Intel only — GUID: dug1619502478466
Ixiasoft
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.2.1. Intel® Agilex™ 7 for F-Series and I-Series I/O Sub-bank Interconnects
3.2.2. Intel® Agilex™ 7 for F-Series and I-Series Input DQS/Strobe Tree
3.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ 7 for F-Series and I-Series FPGA IP Top Level Interfaces
3.2.4. Dynamic Reconfiguration
3.2.5. I/O Timing
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
Visible to Intel only — GUID: dug1619502478466
Ixiasoft
3.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
The complete range is from 0 to 511 in steps of T_vco/256, but the whole range is not always available. Also, only a portion of this range is usable depending on PLL frequency, temperature, and voltage. To find the usable range, perform the write and read-back operations to ensure if the value applies or needs to lower.
Assume the usable range has a maximum value of k and you write a value A. You can read back the value based on the following conditions:
- If A < k, the value you write is under the upper limit, you read back the same value (readdata=A).
- If A > k, the value you write is over the upper limit, you read back the upper limit value. (readdata=k).