PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/10/2023
Public

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2.2.2.3. Register Map

The address register map addr_map.vh and a corresponding C header file are automatically created at IP generation. It contains the Avalon® memory-mapped interface registers that users can read and write to use the AXI4-Lite IP interface of the Calibration IP.

Since these registers include multiple fields for different settings, they should only be changed with read-modify-write cycle to ensure that other fields in the register remain intact. The address of a register is 24 bits, consists of an 11-bit base address right-padded with 13’b0, and a 13-bit offset address left-padded with 11’b0. The padding is done to make the base address and offset address 24 bits.

In the hardware, the addresses are automatically right-shifted to right by 2 bits. In other words, from software view the 24 bits addresses are padded by two zeros at the right. In the hardware view, the zero paddings are discarded and the address width gets reduced to 22 bits.

The base address is calculated as:

Base address = {3’b011, 3 bits instance ID, 2 bits atom ID, 3 bits lane ID},

where atom ID is 2’b00 for Byte control and 2’b01 for Byte. All the reconfigurable PHY Lite for Parallel Interfaces IP settings are in Byte control. The offset voltage for different registers in the address map, as well as bit-field description of the registers, is provided in the table below. As an example, suppose that the PHY Lite for Parallel Interfaces Instance ID is 0 and group 0 is assigned to lane 0. To change the output delay of pin 0, you need to modify the INSTANCE_0_GROUP_0_PIN_00_DDRCRTIMINGCONTROL register.

The base and offset addresses are derived as:

Base address = {3’b011, 3’b000, 2’b00, 3’b000, 13’b0} = 24’h600000

Offset address = {11’b0, 0x100} = 24’h000100

Full address = Base address + Offset address = 24’h0060_0100

An attempt to write to an invalid memory address leads to data corruption in other registers. For guidance, refer to the following table of Avalon® memory-mapped interface address registers. The Avalon® memory-mapped interface registers are 32-bit wide.

Table 13.  Address Register MapThis table shows the relevant bit-fields in the registers as they appear in the generated address map.
Register Name

Offset address

(11 bit)

Description Bit field Bit field Description
INSTANCE_<n>_GROUP_<n>_PIN_00_DDRCRTIMINGCONTROL 0x100 DQ and DQS timing [31:21] TxDqDelay
INSTANCE_<n>_GROUP_<n>_PIN_01_DDRCRTIMINGCONTROL 0xfc
INSTANCE_<n>_GROUP_<n>_PIN_02_DDRCRTIMINGCONTROL 0xf8
INSTANCE_<n>_GROUP_<n>_PIN_03_DDRCRTIMINGCONTROL 0xf4
INSTANCE_<n>_GROUP_<n>_PIN_04_DDRCRTIMINGCONTROL 0xf0 [13:7] RxDqsNDelayPi
INSTANCE_<n>_GROUP_<n>_PIN_05_DDRCRTIMINGCONTROL 0xec
INSTANCE_<n>_GROUP_<n>_PIN_06_DDRCRTIMINGCONTROL 0xe8
INSTANCE_<n>_GROUP_<n>_PIN_07_DDRCRTIMINGCONTROL 0xe4
INSTANCE_<n>_GROUP_<n>_PIN_08_DDRCRTIMINGCONTROL 0xe0 [6:0] RxDqsPDelayPi
INSTANCE_<n>_GROUP_<n>_PIN_09_DDRCRTIMINGCONTROL 0xdc
INSTANCE_<n>_GROUP_<n>_PIN_10_DDRCRTIMINGCONTROL 0xd8
INSTANCE_<n>_GROUP_<n>_PIN_11_DDRCRTIMINGCONTROL 0xd4
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_RCVEN 0x114 RcvEn delay for upper nibble [10:0] RxRcvEnPiRank0
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_RCVEN 0x11c RcvEn delay for lower nibble [10:0] RxRcvEnPiRank0
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_DATACONTROL2 0x10c DQ/DQS ODT, DQ sense amp delay and duration upper nibble [31:27] DqsSenseAmpDelay
[26:23] DqSenseAmpDuration
[22:18] DqSenseAmpDelay
[17:14] DqOdtDuration
[13:9] DqOdtDelay
[8:5] DqsOdtDuration
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_DATACONTROL2 0x110 DQ/DQS ODT, DQ sense amp delay and duration lower nibble [31:27] DqsSenseAmpDelay
[26:23] DqSenseAmpDuration
[22:18] DqSenseAmpDelay
[17:14] DqOdtDuration
[13:9] DqOdtDelay
[8:5] DqsOdtDuration
[4:0] DqsOdtDelay
INSTANCE_<n>_PHY_LANE_<n>_UPPER_NIBBLE_DQSSENSEAMPDURATION 0x124 Dqs sense amp duration upper nibble [29:26] DqsSenseAmpDuration
INSTANCE_<n>_PHY_LANE_<n>_LOWER_NIBBLE_DQSSENSEAMPDURATION 0x128 Dqs sense amp duration lower nibble [29:26] DqsSenseAmpDuration
INSTANCE_<n>_PHY_LANE_<n>_RXFIFO 0x13c Read enable offset change read valid delay [3:0] read_enable_offset
INSTANCE_<n>_PHY_LANE_<n>_DATATRAINFEEDBACK 0x160 Train reset and training mode [14] TrainReset
[9] RLTrainingMode
INSTANCE_<n>_PHY_LANE_<n>_TRAINFEEDBACK 0x1f4 Train feedback [23:12] DataTrainFeedback_N1
[11:0] DataTrainFeedback_N0
INSTANCE_<n>_PHY_LANE_<n>_DATACONTROL6 0x130 VRef I/O Voltage [29:21] RxDataVrefL
[20:12] RxDataVrefU