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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.2.1. Intel® Agilex™ 7 for F-Series and I-Series I/O Sub-bank Interconnects
3.2.2. Intel® Agilex™ 7 for F-Series and I-Series Input DQS/Strobe Tree
3.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ 7 for F-Series and I-Series FPGA IP Top Level Interfaces
3.2.4. Dynamic Reconfiguration
3.2.5. I/O Timing
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
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3.3.2.1. Clock and Reset Interface Signals
Signal Name | Direction | Width | Description |
---|---|---|---|
ref_clk | Input | 1 | Reference clock for the PLL. The reference clock must be synchronous with group_strobe_in to ensure the dqs_enable signal is in-sync with group_strobe_in. |
reset_n | Input | 1 | Resets the interface. Deassertion of this signal should be synchronous to the ref_clk. |
interface_locked | Output | 1 | Interface locked signal from PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP to the core logic. This signal indicates that the PLL and PHY circuitry are locked. Data transfer should starts after the assertion of this signal. |
core_clk_out | Output | 1 | Use this core clock in the core-to-periphery transfer of soft logic data and control signals. The core_clk_out frequency depends on the interface frequency and clock rate of user logic parameter. |