PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/10/2023
Public

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2.4. I/O Standards

The PHY Lite for Parallel Interfaces IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups. One RZQ group supports up to two different output terminations and one input termination. RZQ pin cannot be used as data pin.

Table 18.  I/O Standards and Termination Values for Intel® Agilex™ M-Series Devices
I/O Standard Valid Input Terminations (Ω) Input Terminations without Calibration (Ω) Valid Output Terminations (Ω) Output Terminations without Calibration (Ω) RZQ (Ω)
SSTL-12 50, 60 50 34, 40 34, 40 240
1.2-V POD 40, 50, 60 50 34, 40 34, 40 240
1.1-V POD 40, 50, 60 50 34, 40 34, 40 240
1.2-V HSTL 50, 60 50 34, 40 34, 40 100
1.2-V HSUL 34, 40 34, 40 240
1.1-V LVSTL 40, 50, 60 50 34, 40 34, 40 240
1.05-V LVSTL 40, 50, 60 50 34, 40 34, 40 240