PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 4/10/2023
Public

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2.2.1.1.1. Clock Frequency Relationships

Equation 1. Relationships Between Clock Domains in PHY Lite for Parallel Interfaces IPThese equations describe the relationships between the clock domains available in the PHY Lite for Parallel Interfaces IP.

Core Clock Rate (PHYLITE_IN_RATE) = Interface clock frequency / Core clock frequency

VCO frequency Multiplier Factor (PHYLITE_OUT_RATE) = VCO clock frequency / Interface clock frequency