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1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
3.2.1. Intel® Agilex™ 7 for F-Series and I-Series I/O Sub-bank Interconnects
3.2.2. Intel® Agilex™ 7 for F-Series and I-Series Input DQS/Strobe Tree
3.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ 7 for F-Series and I-Series FPGA IP Top Level Interfaces
3.2.4. Dynamic Reconfiguration
3.2.5. I/O Timing
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration
4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
4.5.6.4.5. I/O Timing Violation
4.5.6.4.6. Internal FPGA Path Timing Violation
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration
5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints
5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints
5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data
5.5.6.4.5. I/O Timing Violation
5.5.6.4.6. Internal FPGA Path Timing Violation
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4.5.1. Guidelines: Group Pin Placement
Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP group pins.
- All groups in a PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP must be placed across a contiguous set of lanes. The number of lanes depends on the number of pins used by the group.
- Two groups, from either the same or different PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP, cannot share an I/O lane.
- For PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP instance that spans more than one I/O bank, all groups in the interface must be placed across a contiguous set of banks within an I/O column. The number of I/O banks required depends on the memory interface width.
- Pins that are not used in an I/O bank are available as general purpose I/O (GPIO) pins.
- To constrain groups from separate PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies, and the same voltage settings.
- A reference clock network can only span across maximum of 6 I/O banks.
- You cannot share the OCT termination block across the I/O column. You can associate the terminated pins of the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP instance with an RZQ pin through RZQ_GROUP assignment.
Number of Pins in Group | Valid DQS Group in a Bank | Valid Index in a Bank |
---|---|---|
1-12 | DQS for X8/X9 | {0-11}/{12-23}/{24-35}/{36-47} |
13-24 | DQS for X16/X18 | {0-23}/{24-47} |
25-48 | DQS for X32/X36 | {0-47} |
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