Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

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6.6.4.3. Reset Sequencer CSR Registers

The Reset Sequencer's CSR registers provide the following functionality:

  • Support reset logging
    • Ability to identify which reset is asserted.
    • Ability to determine whether any reset is currently active.
  • Support software triggered resets
    • Ability to generate reset by writing to the register.
    • Ability to disable assertion or deassertion sequence.
  • Support software sequenced reset
    • Ability for the software to fully control the assertion/deassertion sequence by writing to registers and stepping through the sequence.
  • Support reset override
    • Ability to assert a specific component reset through software.
Table 87.  Reset Sequencer CSR Register Map
Register Offset Width Reset Value Description
Status Register 0x00 32 0x0 The Status register indicates which sources are allowed to cause a reset.
Interrupt Enable Register 0x04 32 0x0 The Interrupt Enable register bits enable events triggering the IRQ of the reset sequencer.
Control Register 0x08 32 0x0 The Control register allows you to control the Reset Sequencer.
Software Sequenced Reset Assert Control Register 0x0C 32 0x3FF You can program the Software Sequenced Reset Assert control register to control the reset assertion sequence.
Software Sequenced Reset Deassert Control Register 0x10 32 0x3FF You can program the Software Sequenced Reset Deassert register to control the reset deassertion sequence.
Software Direct Controlled Resets 0x14 32 0X0 You can write a bit to 1 to assert the reset_outN signal, and to 0 to deassert the reset_outN signal.
Software Reset Masking 0x18 32 0x0 Masking off (writing 1) to a reset_outN "Reset Mask Enable" signal prevents the corresponding reset from being asserted. Writing a bit to 0 to a reset mask enable signal allows assertion of reset_outN.