Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

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Document Table of Contents

7.8.1. Avalon® Packets to Transactions Converter IP Interfaces

Table 187.  Properties of Avalon® Streaming Interfaces

Feature

Property

Backpressure

Ready latency = 0.

Data Width

Data width = 8 bits; Bits per symbol = 8.

Channel

Not supported.

Error

Not used.

Packet

Supported.

The Avalon® memory mapped host interface supports read and write transactions. The data width is set to 32 bits, and burst transactions are not supported.