Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

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6.4.2.1. IRQ Bridge

The IRQ Bridge Intel® FPGA IP allows you to route interrupt wires between Platform Designer subsystems.
Figure 215.  Platform Designer IRQ Bridge ApplicationThe peripheral subsystem example below has three interrupt senders that are exported to the top-level of the subsystem. The interrupts are then routed to the CPU subsystem using the IRQ bridge.

Note: Nios® II BSP tools support the IRQ Bridge. Interrupts connected via an IRQ Bridge appear in the generated system.h file. You can use the following properties with the IRQ Bridge, which do not effect Platform Designer interconnect generation. Platform Designer uses these properties to generate the correct IRQ information for downstream tools:
  • set_interface_property <sender port> bridgesToReceiver <receiver port> — The <sender port> of the IP generates a signal that is received on the IP's <receiver port>. Sender ports are single bits. Receive ports can be multiple bits. Platform Designer requires the bridgedReceiverOffset property to identify the <receiver port> bit that the <sender port> sends.
  • set_interface_property <sender port> bridgedReceiverOffset <port number> — Indicates the <port number> of the receiver port that the <sender port> sends.