Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

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Document Table of Contents

2.24. Creating a System with Platform Designer Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2022.12.12 22.4
  • Updated What's New in This Version topic for board-aware flow support.
  • Revised Creating or Opening a Platform Designer System topic to reference board-aware GUI.
  • Updated Specifying the Target Intel® FPGA Device or Board for a System topic for board-aware GUI.
  • Added new Using the Board-Aware Flow in Platform Designer section.
  • Added new Creating IP Presets Targeting Specific Boards section.
  • Removed limitation statement about no support for assertion monitors in Questa* - Intel® FPGA Edition simulator. This simulator does support assertion monitors.
2022.09.26 22.3
  • Added clarifying note about the default agent selection to Specifying a Default Avalon Agent or AXI Subordinate topic.
  • Updated screenshot in Specifying Interconnect Parameters topic for new Response FIFO Type option.
  • Revised Interconnect Parameters topic for new Response FIFO Type option.
2022.06.20 22.2
  • Updated What's New In This Version topic for latest changes in Platform Designer.
2022.04.02 22.1
  • Added Top FAQs navigation and What's New In This Version topic.
  • Added new Correcting Platform Designer System Timing Issues topic.
  • Updated entire chapter for new AXI "manager" and AXI "subordinate" replacement terms. Refer to the AMBA® AXI and ACE Protocol Specification.
2021.10.04 21.3
  • Added new Preserving a System Module, Interface, or Port for Debugging topic.
  • Added new Changing the Platform Designer Font topic.
  • Added new Comparing Platform Designer Systems and IP Components section.
  • Updated Generation Dialog Box Options topic note for Questa* - Intel® FPGA Edition simulator.
  • Added references to the Nios® V processor and documentation throughout.
2021.03.29 21.1
  • Converted to "host" and "agent" inclusive terminology for Avalon® memory mapped interface descriptions and related GUI elements throughout.
  • Added new Saving and Archiving Platform Designer Systems overview.
  • Revised Saving Platform Designer Systems for more detail, screenshot, and links about Export System as Platform Designer script (.tcl).
  • Revised Archiving Platform Designer Systems for more detail, screenshots, and links about using qsys-archive command.
  • Added new Including Platform Designer Systems in Project Archives topic.
  • Added new Project Files to Include in External Revision Control topic.
  • Updated Generation Dialog Box Options topic for new simulation options.
  • Updated Simulating Platform Designer Systems for new simulation options and images.
2020.12.14 20.4
  • Updated "Specifying Interconnect Parameters" topic for latest GUI options and methods.
  • Updated "Interconnect Parameters" table for latest parameters and names.
  • Updated all System View tab screenshots for latest filter options.
  • Referenced Linux limitation for HLS generic component types.
  • Revised "Files generated for IP cores and Platform Designer Systems" diagram variable names.
2020.09.28 20.3
  • Removed reference to obsolete Read/Write Waveforms option from "Modifying IP Parameters" topic.
  • Removed reference to obsolete System Information tab and Implementation Templates tab from "Specifying IP Component Instantiation Options" topic.
  • Removed reference to obsolete Direction option from "Changing a Conduit to a Reset" topic.
  • Added details about filter controls to "Filtering the System View" topic.
2020.01.31 19.1
  • Removed obsolete "Implementing Performance Monitoring" topic.
2019.10.02 19.1
  • Updated location of interconnect parameters security setting in "Configuring Platform Designer System Security" topic.
2019.09.30 19.1
  • Removed reference to obsolete Bus Analyzer Toolkit from "Implementing Performance Monitoring" topic.
2019.06.24 19.1
  • Removed obsolete Interconnect Type parameter from "Interconnect Parameters" topic.
2019.04.30 19.1
  • Corrected typographical error in "Interconnect Parameters" topic.
2019.04.01 19.1
  • Described new Domains tab for specifying system-wide or domain-specific interconnect parameters.
  • Described new default use of synchronous reset option for Intel® Stratix® 10 designs in "Interconnect Parameters."
  • Described new Schematic tab in "Previewing the System Interconnect."
2018.12.15 18.1
  • Replaced references to System Contents tab with new System View tab.
  • Described new Filter tab in Filtering the "Filtering the System View."
  • Updated "Disabling or Enabling Parallel IP Generation" to indicate option is now on by default and describe optional settings.
  • Moved command-line utility information into new "Platform Designer Command-Line Interface" chapter.
  • Removed "Creating a Combined Simulation Script" topic that does not apply to Platform Designer.
  • Revised headings and re-organized content into user task-based sections.
  • Updated screenshots for latest version.
2018.09.24 18.1
  • Removed duplicated topic: Manually Control Pipelining in the Platform Design Interconnect. The topic is now in the Platform Design Interconnect chapter.
  • Added statement about supported standards for IP-XACT.
  • Divided topic: Specify Implementation Type for IP Components into Configure the System Representation of an IP Core and Implementation Type.
  • Reorganized information about associating Intel Quartus Prime projects to Platform Designer systems.
  • Grouped information regarding definition and management of IP cores in Platform Designer under topic: IP Cores in Platform Designer, and updated contents.
  • Expanded description of parallel IP generation.
  • In topic 64-Bit Addressing Support, added link to information about the auto base assignment feature.
2018.06.15 18.0
  • Updated description of Enable ECC protection in table: System-Wide Interconnect Requirements.
  • Updated example in topic: Generate a Platform Design System with qsys-script.
2018.05.07 18.0
  • Added support for hierarchical simscripts, and the Xcelium™ Parallel Simulator in .
  • Added support for --debug command used with qsys-edit.
  • Added support for wire-level expressions and connectivity.
  • Added _hw.tcl commands to support wire-level expressions.
2017.11.06 17.1
  • Changed instances of Qsys Pro to Platform Designer
2017.05.06 17.0
  • Updated the topic - Create/Open Project in Qsys Pro
  • Updated the topic - Modify the Target Device
  • Updated the topic - Modify the IP Search Path
  • Added new topic - Save your System
  • Added new topic - Archive your System
  • Added new topic - Synchronize IP File References
  • Updated the topic - Upgrade Outdated IP Components in Qsys Pro.
  • Added new topic - Run System Scripts
  • Added new topic - View Avalon Memory Mapped Domains in Your Qsys Pro System
  • Updated the topic - Qsys Pro Scripting Command Reference for new Tcl scripting commands
  • Updated the topic - Qsys Pro Scripting Property Reference for new Tcl scripting property
2016.10.31 16.1
  • Implemented Intel rebranding.
  • Implemented Qsys rebranding.
  • Integrated Qsys Pro chapter with Qsys.
  • Added command-line options for qsys-archive.
  • Added command-line options for quartus_ipgenerate.
  • Updated the Qsys Pro scripting commands.
  • Added topic on Qsys Pro design conversion.
2016.05.03 16.0
  • Qsys Command-Line Utilities updated with latest supported command-line options.
  • Added: Generate Header Files
2015.11.02 15.1
  • Added: Troubleshooting IP or Qsys Pro System Upgrade.
  • Added: Generating Version-Agnostic IP and Qsys Pro Simulation Scripts.
  • Changed instances of Quartus II to Quartus Prime.
2015.05.04 15.0
  • New figure: Avalon Memory Mapped Write Host Timing Waveforms in the Parameters Tab.
  • Added Enable ECC protection option, Specify Qsys Interconnect Requirements.
  • Added External Memory Interface Debug Toolkit note, Generate a Qsys System.
  • Modelsim-Altera now supports native mixed-language (VHDL/Verilog/SystemVerilog) simulation, Generating Files for Synthesis and Simulation.
December 2014 14.1
  • Create and Manage Hierarchical Qsys Systems.
  • Schematic tab.
  • View and Filter Clock and Reset Domains.
  • File > Recent Projects menu item.
  • Updated example: Hierarchical System Using Instance Parameters
August 2014 14.0a10
  • Added distinction between legacy and standard device generation.
  • Updated: Upgrading Outdated IP Components.
  • Updated: Generating a Qsys System.
  • Updated: Integrating a Qsys System with the Quartus II Software.
  • Added screen shot: Displaying Your Qsys System.
June 2014 14.0
  • Added tab descriptions: Details, Connections.
  • Added Managing IP Settings in the Quartus II Software.
  • Added Upgrading Outdated IP Components.
  • Added Support for Avalon Memory Mapped Non-Power of Two Data Widths.
November 2013 13.1
  • Added Integrating with the .qsys File.
  • Added Using the Hierarchy Tab.
  • Added Managing Interconnect Requirements.
  • Added Viewing Qsys Interconnect.
May 2013 13.0
  • Added AMBA APB support.
  • Added qsys-generate utility.
  • Added VHDL BFM ID support.
  • Added Creating Secure Systems (TrustZones) .
  • Added CMSIS Support for Qsys Systems With An HPS Component.
  • Added VHDL language support options.
November 2012 12.1
  • Added AMBA AXI4 support.
June 2012 12.0
  • Added AMBA AX3I support.
  • Added Preset Editor updates.
  • Added command-line utilities, and scripts.
November 2011 11.1
  • Added Synopsys VCS and VCS MX Simulation Shell Script.
  • Added Cadence Incisive Enterprise (NCSIM) Simulation Shell Script.
  • Added Using Instance Parameters and Example Hierarchical System Using Parameters.
May 2011 11.0
  • Added simulation support in Verilog HDL and VHDL.
  • Added testbench generation support.
  • Updated simulation and file generation sections.
December 2010 10.1 Initial release.