Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

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Document Table of Contents

6.6.4.4.2. Reset Assert Flow

The following flow sequence occurs for a Reset Assert Flow:

  • A reset is triggered either by the software, or when input resets to the Reset Sequencer are asserted.
  • The IRQ is asserted, if the IRQ is enabled.
  • Software reads the Status register to determine which reset was triggered.