Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.6.2. Arbitration Shares and Bursts

Arbitration shares provide control over the arbitration process. By default, the arbitration algorithm allocates evenly, with all hosts receiving one share.

You can adjust the arbitration process by assigning a larger number of shares to hosts that need greater throughput. The larger the arbitration share, the more transfers are allocated to the host to access an agent. The hosts gets uninterrupted access to the agent for its number of shares when the host is reading or writing.

If a host cannot post a transfer, and other hosts are waiting to gain access to a particular agent, the arbiter grants access to another host. This mechanism prevents a host from wasting arbitration cycles if it cannot post back-to-back transfers. A bursting transaction contains multiple beats (or words) of data, starting from a single address. Bursts allow a host to maintain access to an agent for more than a single word transfer. If a bursting host posts a write transfer with a burst length of eight, it is guaranteed arbitration for eight write cycles.

You can assign arbitration shares to an Avalon® memory mapped bursting host and AXI hosts (which are always considered a bursting host). Each share consists of one burst transaction (such as multi cycle write), and allows a host to complete a number of bursts before arbitration switches to the next host.