Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

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6.10.6.1. AXI and Avalon® Ordering

There is a potential read-after-write risk when Avalon® hosts transact to AXI subordinates.

According to the AMBA* Protocol Specifications, there is no ordering requirement between reads and writes. However, Avalon® has an implicit ordering model that requires transactions from a host to the same AXI subordinate to be in order. The Avalon® interconnect always processes the transactions in order. The interconnect blocks transactions if required. The interconnect prevents writing to the AXI subordinate when read is pending.