Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

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6.5.1.2.4. HSSI Bonded Clock Example

HSSI Bonded Clock Interface Example

You can make connections to declare the HSSI Bonded Clock interfaces in the _hw.tcl file.

package require -exact qsys 14.0

set_module_property name hssi_bonded_component
set_module_property ELABORATION_CALLBACK elaborate

add_fileset synthesis QUARTUS_SYNTH generate
add_fileset verilog_simulation SIM_VERILOG generate

set_fileset_property synthesis TOP_LEVEL "hssi_bonded_component"

set_fileset_property verilog_simulation TOP_LEVEL \
"hssi_bonded_component"

proc elaborate {} {
	add_interface my_clock_start hssi_bonded_clock start
	set_interface_property my_clock_start  ENABLED true

	add_interface_port my_clock_start  hssi_bonded_clock_port_out \
 clk Output 1024

	add_interface my_clock_end hssi_bonded_clock end
	set_interface_property my_clock_end  ENABLED true

	add_interface_port my_clock_end  hssi_bonded_clock_port_in \
 clk Input 1024
}

proc generate { output_name } {
	add_fileset_file hssi_bonded_component.v VERILOG PATH \
 "hssi_bonded_component.v"}

If you use the components in a hierarchy, for example, instantiated in a composed component, you can declare the connections as illustrated in this example.

HSII Bonded Clock Instantiated in a Composed Component

add_instance myinst1 hssi_bonded_component
add_instance myinst2 hssi_bonded_component
# add connection from source of myinst1 to sink of myinst2

add_connection myinst1.my_clock_start myinst2.my_clock_end \
hssi_bonded_clock

# adding connection from source of myinst2 to sink of myinst1
 
add_connection myinst2.my_clock_start myinst2.my_clock_end \
hssi_bonded_clock