Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

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5.6.2.2.1. Simple Avalon® Memory Mapped Interfaces

Simple interface transfers do not support pipelining or bursting for reads or writes; consequently, their performance is limited. Simple interfaces are appropriate for transfers between hosts and infrequently used agent interfaces. In Platform Designer, the PIO, UART, and Timer include agent interfaces that use simple transfers.