Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/12/2022
Public

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7.11.5. Avalon® Streaming Single Clock and Dual Clock FIFO IP Parameters

Table 191.   Avalon® Streaming Single Clock FIFO IP Parameters

Parameter

Legal Values

Description

Symbols per beat

1–32

These parameters determine the width of the FIFO.

FIFO width = Bits per symbol * Symbols per beat, where: Bits per symbol is the number of bits in a symbol, and Symbols per beat is the number of symbols transferred in a beat.

Bits per symbol

1–32

FIFO depth

2 n

The FIFO depth. An output pipeline stage is added to the FIFO to increase performance, which increases the FIFO depth by one. <n> = n=1,2,3,4 and so on.

Channel width

1–32

The width of the channel signal.

Error width

0–32

The width of the error signal.

Use packets

On|Off

Turn on this parameter to enable data packet support on the Avalon® streaming data interfaces.

Use fill level

On|Off

Turn on this parameter to include the Avalon® memory mapped control and status register interface (CSR). The CSR is enabled when Use fill level is set to 1.

Use store and forward

On|Off

To turn on Cut-through mode, Use store and forward must be set to 0. Turning on Use store and forward prompts the user to turn on Use fill level, and then the CSR appears.
Use almost full status

On|Off

Enables a single-bit almost-full status streaming interface
Use almost empty status

On|Off

Enables a single-bit almost-empty status streaming interface.

Enable explicit maxChannel

On|Off

Turn on this parameter to specify the maximum channel number.

Explicit maxChannel

value

Maximum channel number.

Use synchronous resets

On|Off

Turing off allows asynchronous resets. Turning on uses internal reset synchronization.

Table 192.   Avalon® Streaming Dual Clock FIFO IP Parameters

Parameter

Legal Values

Description

Symbols per beat

1–32

These parameters determine the width of the FIFO.

FIFO width = Bits per symbol * Symbols per beat, where: Bits per symbol is the number of bits in a symbol, and Symbols per beat is the number of symbols transferred in a beat.

Bits per symbol

1–32

FIFO depth

2 n

The FIFO depth. An output pipeline stage is added to the FIFO to increase performance, which increases the FIFO depth by one. <n> = n=1,2,3,4 and so on.

Channel width

1–32

The width of the channel signal.

Error width

0–32

The width of the error signal.

Use packets

On|Off

Turn on this parameter to enable data packet support on the Avalon® streaming data interfaces.

Use sink fill level

On|Off

Turn on this parameter to include the Avalon® memory mapped control and status register interface in the input clock domain.

Use source fill level

On|Off

Turn on this parameter to include the Avalon® memory mapped control and status register interface in the output clock domain.

Write pointer synchronizer length

2–8

The length of the write pointer synchronizer chain. Setting this parameter to a higher value leads to better metastability while increasing the latency of the IP.

Read pointer synchronizer length

2–8

The length of the read pointer synchronizer chain. Setting this parameter to a higher value leads to better metastability.

Enable explicit maxChannel

On|Off

Turn on this parameter to specify the maximum channel number.

Explicit maxChannel

value

Maximum channel number.

Pipeline pointers

On|Off

This option enables the pipeline pointer after clock domain crossing. Enable this option for better timing closure by adding one clock cycle of latency.

Use synchronous resets

On|Off

Turing off allows asynchronous resets. Turning on uses internal reset synchronization.

Note: For more information about metastability in Intel devices, refer to Understanding Metastability in FPGAs. For more information about metastability analysis and synchronization register chains, refer to the Managing Metastability in the Intel Quartus Prime Pro Edition User Guide: Design Recommendations.