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Ixiasoft
1. Answers to Top FAQs
2. Creating a System with Platform Designer
3. Creating a Board Support Package with BSP Editor
4. Creating Platform Designer Components
5. Optimizing Platform Designer System Performance
6. Platform Designer Interconnect
7. Platform Designer System Design Components
8. Platform Designer Command-Line Utilities
9. Component Interface Tcl Reference
10. Intel® Quartus® Prime Pro Edition User Guide: Platform Designer Document Archives
A. Intel® Quartus® Prime Pro Edition User Guides
2.1. What's New In This Version
2.2. Platform Designer Interface Support
2.3. Platform Designer System Design Flow
2.4. Creating or Opening a Platform Designer System
2.5. Using the Board-Aware Flow in Platform Designer
2.6. Viewing a Platform Designer System
2.7. Adding IP Components to a System
2.8. Connecting System Components
2.9. Specifying Interconnect Parameters
2.10. Correcting Platform Designer System Timing Issues
2.11. Specifying Signal and Interface Boundary Requirements
2.12. Configuring Platform Designer System Security
2.13. Upgrading Outdated IP Components in Platform Designer
2.14. Synchronizing System Component Information
2.15. Validating System Integrity
2.16. Preserving System Elements for Debug
2.17. Generating a Platform Designer System
2.18. Generating Simulation Files for Platform Designer Systems and IP Variants
2.19. Adding a System to an Intel® Quartus® Prime Project
2.20. Managing Hierarchical Platform Designer Systems
2.21. Saving and Archiving Platform Designer Systems
2.22. Comparing Platform Designer Systems and IP components
2.23. Running System Scripts
2.24. Creating a System with Platform Designer Revision History
2.6.1. Viewing the System Hierarchy
2.6.2. Filtering the System View
2.6.3. Viewing System Connections
2.6.4. Viewing Clock and Reset Domains
2.6.5. Viewing Avalon® Memory-Mapped Domains in a System
2.6.6. Viewing the System Schematic
2.6.7. Customizing the Platform Designer Layout
2.6.8. Changing the Platform Designer Font
2.17.1. Generation Dialog Box Options
2.17.2. Specifying the Generation ID
2.17.3. Disabling or Enabling Parallel IP Generation
2.17.4. Files Generated for Platform Designer Systems
2.17.5. Generating System Testbench Files
2.17.6. Generating Example Designs for IP Components
2.17.7. Incremental System Generation Example
2.17.8. Generating the HPS IP Component System View Description File
2.17.9. Generating Header Files for Host Components
4.1. Platform Designer Components
4.2. Design Phases of an IP Component
4.3. Creating IP Components in the Component Editor
4.4. Creating Generic Components in a System
4.5. Exporting HDL Parameters to a System
4.6. Scripting Wire-Level Expressions
4.7. Control Interfaces Dynamically with an Elaboration Callback
4.8. Control File Generation Dynamically with Parameters and a Fileset Callback
4.9. Create a Composed Component or Subsystem
4.10. Add Component Instances to a Static or Generated Component
4.11. Creating Platform Designer Components Revision History
4.3.1. Save an IP Component and Create the _hw.tcl File
4.3.2. Edit an IP Component with the Platform Designer Component Editor
4.3.3. Specify IP Component Type Information
4.3.4. Create an HDL File in the Platform Designer Component Editor
4.3.5. Defining HDL Parameters in _hw.tcl
4.3.6. Declaring SystemVerilog Interfaces in _hw.tcl
4.3.7. Create an HDL File Using a Template in the Platform Designer Component Editor
4.3.8. Specify Synthesis and Simulation Files in the Platform Designer Component Editor
4.3.9. Add Signals and Interfaces in the Platform Designer Component Editor
4.3.10. Specify Parameters in the Platform Designer Component Editor
4.3.8.1. Specify HDL Files for Synthesis in the Platform Designer Component Editor
4.3.8.2. Analyze Synthesis Files in the Platform Designer Component Editor
4.3.8.3. Name HDL Signals for Automatic Interface and Type Recognition in the Platform Designer Component Editor
4.3.8.4. Specify Files for Simulation in the Component Editor
4.3.8.5. Include an Internal Register Map Description in the .svd for Agent Interfaces Connected to an HPS Component
4.3.10.1. Valid Ranges for Parameters in the _hw.tcl File
4.3.10.2. Types of Platform Designer Parameters
4.3.10.3. Obtaining Device Trait Information Using PART_TRAIT System Information Parameter
4.3.10.4. Declare Parameters with Custom _hw.tcl Commands
4.3.10.5. Validate Parameter Values with a Validation Callback
5.1. Designing with Avalon® and AXI Interfaces
5.2. Using Hierarchy in Systems
5.3. Using Concurrency in Memory-Mapped Systems
5.4. Inserting Pipeline Stages to Increase System Frequency
5.5. Using Bridges
5.6. Increasing Transfer Throughput
5.7. Reducing Logic Utilization
5.8. Reducing Power Consumption
5.9. Reset Polarity and Synchronization in Platform Designer
5.10. Optimizing Platform Designer System Performance Design Examples
5.11. Optimizing Platform Designer System Performance Revision History
6.1. Memory-Mapped Interfaces
6.2. Avalon® Streaming Interfaces
6.3. Avalon® Streaming Credit Interfaces
6.4. Interrupt Interfaces
6.5. Clock Interfaces
6.6. Reset Interfaces
6.7. Conduits
6.8. Interconnect Pipelining
6.9. Error Correction Coding (ECC) in Platform Designer Interconnect
6.10. AMBA* 3 AXI Protocol Specification Support (version 1.0)
6.11. AMBA* 3 APB Protocol Specification Support (version 1.0)
6.12. AMBA* 4 AXI Memory-Mapped Interface Support (version 2.0)
6.13. AMBA* 4 AXI Streaming Interface Support (version 1.0)
6.14. AMBA* 4 AXI-Lite Protocol Specification Support (version 2.0)
6.15. Port Roles (Interface Signal Types)
6.16. Platform Designer Interconnect Revision History
6.1.1. Platform Designer Packet Format
6.1.2. Interconnect Domains
6.1.3. Avalon Host and AXI Manager Network Interfaces
6.1.4. Avalon Agent and AXI Subordinate Network Interfaces
6.1.5. Arbitration
6.1.6. Memory-Mapped Arbiter
6.1.7. Datapath Multiplexing Logic
6.1.8. Width Adaptation
6.1.9. Burst Adapter
6.1.10. Waitrequest Allowance Adapter
6.1.11. Read and Write Responses
6.1.12. Platform Designer Address Decoding
6.1.3.1. Avalon® Memory Mapped Host Agent
6.1.3.2. Avalon® Memory Mapped Host Translator
6.1.3.3. AXI Manager Agent
6.1.3.4. AXI Translator
6.1.3.5. APB Manager Agent
6.1.3.6. APB Subordinate Agent
6.1.3.7. APB Translator
6.1.3.8. AHB Subordinate Agent
6.1.3.9. Memory-Mapped Router
6.1.3.10. Memory-Mapped Traffic Limiter
6.6.4.3.1. Reset Sequencer Status Register
6.6.4.3.2. Reset Sequencer Interrupt Enable Register
6.6.4.3.3. Reset Sequencer Control Register
6.6.4.3.4. Reset Sequencer Software Sequenced Reset Assert Control Register
6.6.4.3.5. Reset Sequencer Software Sequenced Reset Deassert Control Register
6.6.4.3.6. Reset Sequencer Software Direct Controlled Resets
6.6.4.3.7. Reset Sequencer Software Reset Masking
6.12.1. Burst Support
6.12.2. QoS
6.12.3. Regions
6.12.4. Write Response Dependency
6.12.5. AWCACHE and ARCACHE
6.12.6. Width Adaptation and Data Packing in Platform Designer
6.12.7. Ordering Model
6.12.8. Read and Write Allocate
6.12.9. Locked Transactions
6.12.10. Memory Types
6.12.11. Mismatched Attributes
6.12.12. Signals
6.14.1. AMBA* 4 AXI-Lite Signals
6.14.2. AMBA* 4 AXI-Lite Optional Port Support and Interconnect
6.14.3. AMBA* 4 AXI-Lite Bus Width
6.14.4. AMBA* 4 AXI-Lite Outstanding Transactions
6.14.5. AMBA* 4 AXI-Lite IDs
6.14.6. Connections Between AMBA* 3 AXI, AMBA* 4 AXI and AMBA* 4 AXI-Lite
6.14.7. AMBA* 4 AXI-Lite Response Merging
6.15.1. AXI Manager Interface Signal Types
6.15.2. AXI Subordinate Interface Signal Types
6.15.3. AMBA* 4 AXI Manager Interface Signal Types
6.15.4. AMBA* 4 AXI Subordinate Interface Signal Types
6.15.5. AMBA* 4 AXI-Stream Manager and Subordinate Interface Signal Types
6.15.6. AMBA* 4 AXI-Lite Signal Support and Limitations
6.15.7. APB Interface Signal Types
6.15.8. Avalon® Memory Mapped Interface Signal Roles
6.15.9. Avalon® Streaming Interface Signal Roles
6.15.10. Avalon® Streaming Credit Interface Signal Roles
6.15.11. Avalon® Streaming Credit User Signals
6.15.12. Avalon® Clock Source Signal Roles
6.15.13. Avalon® Clock Sink Signal Roles
6.15.14. Avalon® Conduit Signal Roles
6.15.15. Avalon® Tristate Conduit Signal Roles
6.15.16. Avalon® Tri-State Agent Interface Signal Types
6.15.17. Avalon® Interrupt Sender Signal Roles
6.15.18. Avalon® Interrupt Receiver Signal Roles
7.1. Bridges
7.2. Error Response Slave Intel® FPGA IP
7.3. Tri-State Components
7.4. Avalon® Data Pattern Generator and Checker Intel® FPGA IP
7.5. Avalon® Streaming Splitter Intel® FPGA IP
7.6. Avalon® Streaming Delay Intel® FPGA IP
7.7. Avalon® Streaming Round Robin Scheduler Intel® FPGA IP
7.8. Avalon® Packets to Transactions Converter Intel® FPGA IP
7.9. Avalon® Streaming Pipeline Stage Intel® FPGA IP
7.10. Avalon® Streaming Multiplexer and Demultiplexer Intel® FPGA IP
7.11. Avalon® Streaming Single-Clock and Dual-Clock FIFO Intel® FPGA IP
7.12. Platform Designer System Design Components Revision History
7.1.1. Clock Bridge Intel® FPGA IP
7.1.2. Avalon® Memory Mapped Clock Crossing Bridge Intel® FPGA IP
7.1.3. Avalon® Memory Mapped Pipeline Bridge Intel® FPGA IP
7.1.4. Avalon® Memory Mapped Unaligned Burst Expansion Bridge Intel® FPGA IP
7.1.5. Bridges Between Avalon® and AXI Interfaces
7.1.6. AXI Bridge Intel® FPGA IP
7.1.7. AXI Timeout Bridge Intel® FPGA IP
7.1.8. Address Span Extender Intel® FPGA IP
7.4.4.1. data_source_reset()
7.4.4.2. data_source_init()
7.4.4.3. data_source_get_id()
7.4.4.4. data_source_get_supports_packets()
7.4.4.5. data_source_get_num_channels()
7.4.4.6. data_source_get_symbols_per_cycle()
7.4.4.7. data_source_get_enable()
7.4.4.8. data_source_set_enable()
7.4.4.9. data_source_get_throttle()
7.4.4.10. data_source_set_throttle()
7.4.4.11. data_source_is_busy()
7.4.4.12. data_source_fill_level()
7.4.4.13. data_source_send_data()
7.4.5.1. data_sink_reset()
7.4.5.2. data_sink_init()
7.4.5.3. data_sink_get_id()
7.4.5.4. data_sink_get_supports_packets()
7.4.5.5. data_sink_get_num_channels()
7.4.5.6. data_sink_get_symbols_per_cycle()
7.4.5.7. data_sink_get_enable()
7.4.5.8. data_sink_set enable()
7.4.5.9. data_sink_get_throttle()
7.4.5.10. data_sink_set_throttle()
7.4.5.11. data_sink_get_packet_count()
7.4.5.12. data_sink_get_error_count()
7.4.5.13. data_sink_get_symbol_count()
7.4.5.14. data_sink_get_exception()
7.4.5.15. data_sink_exception_is_exception()
7.4.5.16. data_sink_exception_has_data_error()
7.4.5.17. data_sink_exception_has_missing_sop()
7.4.5.18. data_sink_exception_has_missing_eop()
7.4.5.19. data_sink_exception_signalled_error()
7.4.5.20. data_sink_exception_channel()
7.11.1. Interfaces Implemented in FIFO Cores
7.11.2. Avalon® Streaming FIFO IP Operating Modes
7.11.3. Avalon® Streaming FIFO IP Buffer Fill Level
7.11.4. Almost-Full and Almost-Empty Thresholds to Prevent Overflow and Underflow
7.11.5. Avalon® Streaming Single Clock and Dual Clock FIFO IP Parameters
7.11.6. Avalon® Streaming Single-Clock FIFO IP Registers
8.1. Run the Platform Designer Editor with qsys-edit
8.2. Scripting IP Core Generation
8.3. Board-Aware Flow Scripting Support
8.4. Display Available IP Components with ip-catalog
8.5. Create an .ipx File with ip-make-ipx
8.6. Generate Simulation Scripts
8.7. Generate a Platform Designer System with qsys-script
8.8. Parameterizing an Instantiated IP Core after save_system Command
8.9. Validate the Generic Components in a System with qsys-validate
8.10. Generate an IP Component or Platform Designer System with quartus_ipgenerate
8.11. Generate an IP Variation File with ip-deploy
8.12. Archive and Extract Platform Designer Systems with qsys-archive
8.13. Platform Designer Scripting Command Reference
8.14. Platform Designer Scripting Property Reference
8.15. Platform Designer Command-Line Interface Revision History
8.13.1.1. create_system
8.13.1.2. export_hw_tcl
8.13.1.3. get_device_families
8.13.1.4. get_devices
8.13.1.5. get_module_properties
8.13.1.6. get_module_property
8.13.1.7. get_project_properties
8.13.1.8. get_project_property
8.13.1.9. load_system
8.13.1.10. save_system
8.13.1.11. set_design_id
8.13.1.12. set_module_property
8.13.1.13. set_project_property
8.13.2.1. get_composed_connections
8.13.2.2. get_composed_connection_parameter_value
8.13.2.3. get_composed_connection_parameters
8.13.2.4. get_composed_instance_assignment
8.13.2.5. get_composed_instance_assignments
8.13.2.6. get_composed_instance_parameter_value
8.13.2.7. get_composed_instance_parameters
8.13.2.8. get_composed_instances
8.13.3.1. set_domain_assignment
8.13.3.2. get_domain_assignment
8.13.3.3. get_domain_assignments
8.13.3.4. set_interface_assignment
8.13.3.5. get_interface_assignment
8.13.3.6. get_interface_assignments
8.13.3.7. set_postadaptation_assignment
8.13.3.8. get_postadaptation_assignment
8.13.3.9. get_postadaptation_assignments
8.13.4.1. add_instance
8.13.4.2. apply_instance_preset
8.13.4.3. create_ip
8.13.4.4. add_component
8.13.4.5. duplicate_instance
8.13.4.6. enable_instance_parameter_update_callback
8.13.4.7. get_instance_assignment
8.13.4.8. get_instance_assignments
8.13.4.9. get_instance_documentation_links
8.13.4.10. get_instance_interface_assignment
8.13.4.11. get_instance_interface_assignments
8.13.4.12. get_instance_interface_parameter_property
8.13.4.13. get_instance_interface_parameter_value
8.13.4.14. get_instance_interface_parameters
8.13.4.15. get_instance_interface_port_property
8.13.4.16. get_instance_interface_ports
8.13.4.17. get_instance_interface_properties
8.13.4.18. get_instance_interface_property
8.13.4.19. get_instance_interfaces
8.13.4.20. get_instance_parameter_property
8.13.4.21. get_instance_parameter_value
8.13.4.22. get_instance_parameter_values
8.13.4.23. get_instance_parameters
8.13.4.24. get_instance_port_property
8.13.4.25. get_instance_properties
8.13.4.26. get_instance_property
8.13.4.27. get_instances
8.13.4.28. is_instance_parameter_update_callback_enabled
8.13.4.29. remove_instance
8.13.4.30. set_instance_parameter_value
8.13.4.31. set_instance_parameter_values
8.13.4.32. set_instance_property
8.13.5.1. add_instantiation_hdl_file
8.13.5.2. add_instantiation_interface
8.13.5.3. add_instantiation_interface_port
8.13.5.4. copy_instance_interface_to_instantiation
8.13.5.5. get_instantiation_assignment_value
8.13.5.6. get_instantiation_assignments
8.13.5.7. get_instantiation_hdl_file_properties
8.13.5.8. get_instantiation_hdl_file_property
8.13.5.9. get_instantiation_hdl_files
8.13.5.10. get_instantiation_interface_assignment_value
8.13.5.11. get_instantiation_interface_assignments
8.13.5.12. get_instantiation_interface_parameter_value
8.13.5.13. get_instantiation_interface_parameters
8.13.5.14. get_instantiation_interface_port_properties
8.13.5.15. get_instantiation_interface_port_property
8.13.5.16. get_instantiation_interface_ports
8.13.5.17. get_instantiation_interface_property
8.13.5.18. get_instantiation_interface_properties
8.13.5.19. get_instantiation_interface_sysinfo_parameter_value
8.13.5.20. get_instantiation_interface_sysinfo_parameters
8.13.5.21. get_instantiation_interfaces
8.13.5.22. get_instantiation_properties
8.13.5.23. get_instantiation_property
8.13.5.24. get_loaded_instantiation
8.13.5.25. import_instantiation_interfaces
8.13.5.26. load_instantiation
8.13.5.27. remove_instantiation_hdl_file
8.13.5.28. remove_instantiation_interface
8.13.5.29. remove_instantiation_interface_port
8.13.5.30. save_instantiation
8.13.5.31. set_instantiation_assignment_value
8.13.5.32. set_instantiation_hdl_file_property
8.13.5.33. set_instantiation_interface_assignment_value
8.13.5.34. set_instantiation_interface_parameter_value
8.13.5.35. set_instantiation_interface_port_property
8.13.5.36. set_instantiation_interface_sysinfo_parameter_value
8.13.5.37. set_instantiation_property
8.13.6.1. apply_component_preset
8.13.6.2. get_component_assignment
8.13.6.3. get_component_assignments
8.13.6.4. get_component_documentation_links
8.13.6.5. get_component_interface_assignment
8.13.6.6. get_component_interface_assignments
8.13.6.7. get_component_interface_parameter_property
8.13.6.8. get_component_interface_parameter_value
8.13.6.9. get_component_interface_parameters
8.13.6.10. get_component_interface_port_property
8.13.6.11. get_component_interface_ports
8.13.6.12. get_component_interface_property
8.13.6.13. get_component_interfaces
8.13.6.14. get_component_parameter_property
8.13.6.15. get_component_parameter_value
8.13.6.16. get_component_parameters
8.13.6.17. get_component_project_properties
8.13.6.18. get_component_project_property
8.13.6.19. get_component_property
8.13.6.20. get_loaded_component
8.13.6.21. load_component
8.13.6.22. reload_component_footprint
8.13.6.23. save_component
8.13.6.24. set_component_parameter_value
8.13.6.25. set_component_project_property
8.13.7.1. add_connection
8.13.7.2. auto_connect
8.13.7.3. get_connection_parameter_property
8.13.7.4. get_connection_parameter_value
8.13.7.5. get_connection_parameters
8.13.7.6. get_connection_properties
8.13.7.7. get_connection_property
8.13.7.8. get_connections
8.13.7.9. remove_connection
8.13.7.10. remove_dangling_connections
8.13.7.11. set_connection_parameter_value
8.13.8.1. add_interface
8.13.8.2. get_exported_interface_sysinfo_parameter_value
8.13.8.3. get_exported_interface_sysinfo_parameters
8.13.8.4. get_interface_port_property
8.13.8.5. get_interface_ports
8.13.8.6. get_interface_properties
8.13.8.7. get_interface_property
8.13.8.8. get_interfaces
8.13.8.9. get_port_properties
8.13.8.10. remove_interface
8.13.8.11. set_exported_interface_sysinfo_parameter_value
8.13.8.12. set_interface_port_property
8.13.8.13. set_interface_property
8.13.9.1. set_validation_property
8.13.9.2. sync_sysinfo_parameters
8.13.9.3. validate_component
8.13.9.4. validate_component_interface
8.13.9.5. validate_connection
8.13.9.6. validate_instance
8.13.9.7. validate_instance_interface
8.13.9.8. validate_system
8.13.9.9. validate_component_footprint
8.13.9.10. reload_component_footprint
8.13.10.1. auto_assign_base_addresses
8.13.10.2. auto_assign_irqs
8.13.10.3. auto_assign_system_base_addresses
8.13.10.4. get_parameter_properties
8.13.10.5. lock_avalon_base_address
8.13.10.6. send_message
8.13.10.7. set_use_testbench_naming_pattern
8.13.10.8. unlock_avalon_base_address
8.13.10.9. get_testbench_dutname
8.13.10.10. get_use_testbench_naming_pattern
8.14.1. Connection Properties
8.14.2. Design Environment Type Properties
8.14.3. Direction Properties
8.14.4. Element Properties
8.14.5. Instance Properties
8.14.6. Interface Properties
8.14.7. Message Levels Properties
8.14.8. Module Properties
8.14.9. Parameter Properties
8.14.10. Parameter Status Properties
8.14.11. Parameter Type Properties
8.14.12. Port Properties
8.14.13. Project Properties
8.14.14. System Info Type Properties
8.14.15. Units Properties
8.14.16. Validation Properties
8.14.17. Interface Direction
8.14.18. File Set Kind
8.14.19. Access Type
8.14.20. Instantiation HDL File Properties
8.14.21. Instantiation Interface Duplicate Type
8.14.22. Instantiation Interface Properties
8.14.23. Instantiation Properties
8.14.24. Port Properties
8.14.25. VHDL Type
9.1.1.1. add_interface
9.1.1.2. add_interface_port
9.1.1.3. get_interfaces
9.1.1.4. get_interface_assignment
9.1.1.5. get_interface_assignments
9.1.1.6. get_interface_ports
9.1.1.7. get_interface_properties
9.1.1.8. get_interface_property
9.1.1.9. get_port_properties
9.1.1.10. get_port_property
9.1.1.11. set_interface_assignment
9.1.1.12. set_interface_property
9.1.1.13. set_port_property
9.1.1.14. set_interface_upgrade_map
9.1.5.1. add_documentation_link
9.1.5.2. get_module_assignment
9.1.5.3. get_module_assignments
9.1.5.4. get_module_ports
9.1.5.5. get_module_properties
9.1.5.6. get_module_property
9.1.5.7. send_message
9.1.5.8. set_module_assignment
9.1.5.9. set_module_property
9.1.5.10. add_hdl_instance
9.1.5.11. package
9.1.6.1. add_instance
9.1.6.2. add_connection
9.1.6.3. get_connections
9.1.6.4. get_connection_parameters
9.1.6.5. get_connection_parameter_value
9.1.6.6. get_instances
9.1.6.7. get_instance_interfaces
9.1.6.8. get_instance_interface_ports
9.1.6.9. get_instance_interface_properties
9.1.6.10. get_instance_property
9.1.6.11. set_instance_property
9.1.6.12. get_instance_properties
9.1.6.13. get_instance_interface_property
9.1.6.14. get_instance_parameters
9.1.6.15. get_instance_parameter_property
9.1.6.16. get_instance_parameter_value
9.1.6.17. get_instance_port_property
9.1.6.18. set_connection_parameter_value
9.1.6.19. set_instance_parameter_value
9.1.7.1. add_fileset
9.1.7.2. add_fileset_file
9.1.7.3. set_fileset_property
9.1.7.4. get_fileset_file_attribute
9.1.7.5. set_fileset_file_attribute
9.1.7.6. get_fileset_properties
9.1.7.7. get_fileset_property
9.1.7.8. get_fileset_sim_properties
9.1.7.9. set_fileset_sim_properties
9.1.7.10. create_temp_file
9.2.1. Script Language Properties
9.2.2. Interface Properties
9.2.3. SystemVerilog Interface Properties
9.2.4. Instance Properties
9.2.5. Parameter Properties
9.2.6. Parameter Type Properties
9.2.7. Parameter Status Properties
9.2.8. Port Properties
9.2.9. Direction Properties
9.2.10. Display Item Properties
9.2.11. Display Item Kind Properties
9.2.12. Display Hint Properties
9.2.13. Module Properties
9.2.14. Fileset Properties
9.2.15. Fileset Kind Properties
9.2.16. Callback Properties
9.2.17. File Attribute Properties
9.2.18. File Kind Properties
9.2.19. File Source Properties
9.2.20. Simulator Properties
9.2.21. Port VHDL Type Properties
9.2.22. System Info Type Properties
9.2.23. Design Environment Type Properties
9.2.24. Units Properties
9.2.25. Operating System Properties
9.2.26. Quartus.ini Type Properties
Visible to Intel only — GUID: mwh1409958668970
Ixiasoft
6.8.1. Add Pipeline Stages to the Interconnect Schematic
You can view and enable pipelinable locations in a graphical schematic of the Platform Designer interconnect. The Memory-Mapped Interconnect tab allows you to adjust pipeline connections in the Platform Designer command and response interconnect.
Note: You can specify the Limit interconnect pipeline stages to option to automatically insert from zero to a maximum of four pipeline stages, rather than adding pipeline stages explicitly in the schematic. Use the schematic if you require finer control than the option provides. Add pipelines to the interconnect schematic only for complete systems. When Enable all pipeline stages is set to TRUE, the Limit interconnect pipeline stages to option is disabled, and you cannot edit pipelines in the schematic.
Figure 223. Available Pipeline Locations in Memory Mapped Interconnect Schematic
- In the Platform Designer software, open a system that includes two Avalon® memory mapped pipeline bridge instances, with one instance functioning as the host, and the other instance functioning as the agent.
- Click View > Domains. The Domains tab displays the memory mapped domains in the system.
- Under Interconnect Parameters, ensure that Enable all pipeline stages is set to False. When set to True, this option disables manual pipeline insertion.
Figure 224. Domains Tab
- In the Domains tab, click Show System With Interconnect. The System with Platform Designer Interconnect window displays the available pipeline locations on the Command and Response tabs.
- Specify the placement of pipeline stages in the interconnect schematic:
- To view all locations that can accept a pipeline stage, enable Show Pipelinable Locations.
- To add a pipeline to an available location, right-click the location and enable Pipelined.
- To add pipelines at all available locations, click Add All Pipelines.
- To remove all pipelines you add, click Remove All Pipelines.
- To remove pipelines that have become stale due to changes since enabling a pipeline, click Remove Stale Pipelines. If you make changes to the original system's connectivity after manually pipelining an interconnect, the inserted pipelines may become invalid. Platform Designer displays warning messages when you generate the system if invalid pipeline stages are detected. You can remove invalid pipeline stages with the Remove Stale Pipelines option in the Memory-Mapped Interconnect tab. Do not make changes to the system's connectivity after manual pipeline insertion.
Note: Review manually-inserted pipelines when upgrading to newer versions of Platform Designer. Manually-inserted pipelines in one version of Platform Designer may not be valid in a future version.