Intel® Stratix® 10 SEU Mitigation User Guide

ID 683602
Date 12/30/2022

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Document Table of Contents

1.1. SEU Mitigation Techniques for Intel® Stratix® 10 Devices

Intel® Stratix® 10 SEU mitigation features can benefit the system by:

  • Ensuring the system functions properly all the time
  • Preventing a system malfunction caused by an SEU event.
  • Handling the SEU event if it is critical to the system.
Table 1.  SEU Mitigation Areas and Approaches for Intel® Stratix® 10 Devices
Area SEU Mitigation Approach
Error Detection and Correction You can enable the error detection and correction (EDC) feature for detecting CRAM SEU events and automatic correction of CRAM contents.
Memory block error correction code Intel® Stratix® 10 designs M20K memory blocks with special layout techniques and Error Correction Code (ECC) to reduce SEU Failures in time (FIT) rate to almost zero.
SEU Sensitivity processing You can use sensitivity processing to identify if the SEU on a CRAM bit location is critical or not critical to the function of your compiled FPGA design bitstream file.
Fault injection You can use fault injection feature to validate the system response to the SEU event by changing the CRAM state to trigger an error.
Hierarchical tagging A complementary capability to sensitivity processing and fault injection for reporting SEU and constraining injection to specific portions of design logic.
Triple Modular Redundancy (TMR) You can implement TMR technique on critical logic such as state machines.