Intel® Stratix® 10 SEU Mitigation User Guide

ID 683602
Date 12/30/2022

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Document Table of Contents Component FIT Rates

The Projected SEU FIT by Component report shows FIT for the following components:

  • SRAM embedded memory in embedded processors hard IP and M20K or M10K blocks
  • CRAM used for LUT masks and routing configuration bits
  • LABs in MLAB mode
  • I/O configuration registers, which the FPGA implements differently than CRAM and design flipflops
  • Standard flipflops the design uses in the address and data registers of M20K blocks, in DSP blocks, and in hard IP
  • User flipflops the design implements in logic cells (ALMs or LEs)