Intel® Stratix® 10 SEU Mitigation User Guide

ID 683602
Date 12/30/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.4.1. Hierarchy Tagging

The Intel® Quartus® Prime hierarchy tagging feature allows you to improve design-effective FIT rate by tagging only the critical logic for device operation.

You can also define the system recovery procedure based on knowledge of logic impaired by SEU. This technique reduces downtime for the FPGA and the system in which the FPGA resides. Other advantages of hierarchy tagging are:

  • Increases system stability by avoiding disruptive recovery procedures for inconsequential errors.
  • Allows diverse corrective action for different design logic.

The .smh file contains a mask for design sensitive bits in a compressed format. The Intel® Quartus® Prime software generates the sensitivity mask for the entire design.