Intel® Stratix® 10 SEU Mitigation User Guide

ID 683602
Date 12/30/2022

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2.1. CRAM Error Detection and Correction

Intel® Stratix® 10 devices feature on-chip EDC circuitry to detect soft errors. If an error caused by SEU event is correctable, the Intel® Stratix® 10 FPGA corrects it if you enable the internal scrubbing feature.

Table 2.  Detection and Correction of Error Types
Error Type Detection Correction
Single bit error Yes Yes
Double adjacent errors Yes1
Multiple bit errors Detects up to 8 CRAM bits that fit in a rectangular box of 8 CRAM bits (8x1, 4x2, 1x8 or 2x4 errors)

The following figure shows the EDC operation. For a given Intel® Stratix® 10 device, the total sectors are divided equally into groups. The number of sectors per group are based on Smax, which is the maximum number of sectors allowed to run the EDC operation concurrently in a same thread. The Smax has device dependency. You can get the Smax details in the System Window: the number of thread(s). In this case, Smax = 2, each group runs at a different thread during SEU detection and correction. The first group will run the EDC process at time T0. This is followed by the second and third group at time T1 and T2 respectively, until the last available group. The time duration to complete one cycle of the EDC process for all the groups is the minimum SEU interval of the device.

Figure 1. EDC Operation
Note: For information about the embedded memory ECC feature, refer to the related information.
1 In Intel® Stratix® 10 devices, double adjacent errors are also detected as multiple bit errors.