Intel® Stratix® 10 SEU Mitigation User Guide

ID 683602
Date 12/30/2022

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4.4. Performing Hierarchy Tagging

You define the FPGA regions for tagging by assigning an ASD Region to the location. You can specify an ASD Region value for any portion of your design hierarchy using the Design Partitions Window.

  1. In the Intel® Quartus® Prime software, choose Assignments > Design Partitions Window.
  2. Right-click anywhere in the header row and turn on ASD Region to display the ASD Region column (if it is not already displayed).
  3. Enter the logic sensitivity ID value from 0 to 32 for any partition to assign it to a specific ASD Region.
    The Logic Sensitivity ID represents the sensitivity tag associated with the partition:
    • A sensitivity tag of 1 is the same as no assignment and indicates a basic sensitivity level, which is "region used in design".
    • A sensitivity tag of 0 is reserved and indicates unused CRAM bits. You can explicitly set a partition to 0 to indicate that the partition is not critical. This setting excludes the partition from sensitivity mapping.
    Note: You can use the same sensitivity tag for multiple design partitions.
Figure 7. ASD Region Column in the Design Partitions Window
Compile the design and the Intel® Quartus® Prime software generates sensitivity data as a standard Intel® hex (big endian) .smh file during .sof file generation.