Visible to Intel only — GUID: sss1445236371448
Ixiasoft
Visible to Intel only — GUID: sss1445236371448
Ixiasoft
1.2. Configuration RAM
FPGAs use memory both in user logic (bulk memory and registers) and in Configuration RAM (CRAM). CRAM is the memory loaded with the user's design. The CRAM configures all logic and routing in the device. If an SEU strikes a CRAM bit, the effect can be harmless if the CRAM bit is not in use. However, a functional error is possible if it affects critical internal signal routing or critical lookup table logic bits as part of the user's design.
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