1. Intel® Stratix® 10 SEU Mitigation Overview 2. Intel® Stratix® 10 Mitigation Techniques for CRAM 3. Secure Device Manager ECC Error Detection 4. Intel® Stratix® 10 SEU Mitigation Implementation Guides 5. Advanced SEU Detection Intel® FPGA IP References 6. Intel® Stratix® 10 Fault Injection Debugger References 7. Intel® Stratix® 10 SEU Mitigation User Guide Archives 8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
4.1. Setting SEU_ERROR Pin 4.2. Intel® Quartus® Prime SEU Software Settings 4.3. Enabling Priority Scrubbing 4.4. Performing Hierarchy Tagging 4.5. Programming Sensitivity Map Header File into Memory 4.6. Performing Lookup for Sensitivity Map Header 4.7. Using the Fault Injection Debugger 4.8. Analyzing SEU Errors Using Signal Tap 4.9. Intel® Quartus® Prime Software SEU FIT Reports
18.104.22.168. Architectural Vulnerability Factor
The Single Event Functional Interrupt (SEFI) ratio measures bit errors due to SEU strikes versus functional interrupts. Minimizing this ratio improves SEU mitigation.
10% SEFI factors are A typical specification to deflate the raw FIT to that observed in practice. For reference, the last two columns in the Projected SEU FIT by Component Usage report show AVF deflations for a conservative SEFI of 50% and a moderate SEFI of 25%.
SEFI represents a combination of factors. A utilization + ECC factor of 40% and AVF of 25% thus represents a global SEFI factor of 10%, because 0.4 × 0.25 = 0.1. An end-to-end SEFI factor of 10% is typical for a full design.
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