18.104.22.168. Mitigated FIT
The Projected SEU FIT by Component Usage report's w/ECC column represents the FPGA's lowest guaranteed, provable FIT rate that the Intel® Quartus® Prime software can calculate. ECC does not affect CRAM and flipflop rates; therefore, the data in the w/ECC column for these components is the same as the in Utilized column.
The ECC code strength varies with the device family. In Intel® Stratix® 10 devices, the M20K block can correct up to two errors, and the FIT rate beyond two (not corrected) is small enough to be negligible in the total.
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