Intel® Stratix® 10 SEU Mitigation User Guide

ID 683602
Date 12/30/2022

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Document Table of Contents Off-Chip Lookup Sensitivity Processing

The Advanced SEU Detection IP core reads the error message queue content and presents information to a system processor. The processor determines whether the failure affects the device operation. The system processor implements the algorithm to perform a lookup against the .smh.

Figure 3. System Overview for Off-Chip Lookup Sensitivity Processing with Advanced SEU Detection IP Core

The off-chip lookup sensitivity processing is as follows:

  1. The SEU_ERROR is asserted when there is an SEU error.
  2. The Advanced SEU Detection IP core retrieves the error message from SDM and stores it in the internal FIFO.
    Note: The Advanced SEU Detection IP core asserts sys_error signal if error occurs in system while retrieving the error message.
  3. The Advanced SEU Detection IP core asserts the avst_seu_source_valid signal to indicate an error message is available.
  4. The external sensitivity processor must monitor the avst_seu_source_valid signal of the Advanced SEU Detection IP core. If there is an error message available, the processor can start to read the SEU error through the Avalon® streaming interface and perform lookup against the sensitivity map to determine the criticality of the SEU error.