1. Intel® Stratix® 10 SEU Mitigation Overview 2. Intel® Stratix® 10 Mitigation Techniques for CRAM 3. Secure Device Manager ECC Error Detection 4. Intel® Stratix® 10 SEU Mitigation Implementation Guides 5. Advanced SEU Detection Intel® FPGA IP References 6. Intel® Stratix® 10 Fault Injection Debugger References 7. Intel® Stratix® 10 SEU Mitigation User Guide Archives 8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
4.1. Setting SEU_ERROR Pin 4.2. Intel® Quartus® Prime SEU Software Settings 4.3. Enabling Priority Scrubbing 4.4. Performing Hierarchy Tagging 4.5. Programming Sensitivity Map Header File into Memory 4.6. Performing Lookup for Sensitivity Map Header 4.7. Using the Fault Injection Debugger 4.8. Analyzing SEU Errors Using Signal Tap 4.9. Intel® Quartus® Prime Software SEU FIT Reports
4.3. Enabling Priority Scrubbing
To specify areas for high priority internal scrubbing, use the Intel® Quartus® Prime Logic Lock region and design partition features.
- Open the Chip Planner and Design Partition Planner.
- Click Tools > Design Partition Planner
- Click Tools > Chip Planner
- In the Chip Planner window, go to the Tasks pane, and double-click Report Design Partitions. The Report Design Partitions task causes the Chip Planner to display the physical location of design entities using the same colors that the entities are displayed in the Design Partition Planner.
- In the Design Partition Planner window, drag the entities of interest (entities to be included in the priority scrubbing area) out from their parents. Alternatively, you can right click the entity of interest and click Extract from Parent.
- Create a partition for each of the entity of interest by right-clicking the entity, and clicking Create Design Partition.
- Create a Logic Lock region for each partition by right-clicking the partition and clicking Create Logic Lock Region. Alternatively, you can create a Logic Lock region using the Logic Lock Region window from the Intel® Quartus® Prime menu, Assignments > Logic Lock Regions Window. You can specify the size of the Logic Lock Region by changing the values in Width and Height accordingly. The number of priority SEU sectors depend on the area covered by the Width and Height setting.
- From the Intel® Quartus® Prime menu, select Assignments > Assignment Editor.
- In the Assignment Editor window, assign Priority SEU Area to the design partition where you place the Logic Lock region. Select On for Value and Yes for Enabled.
Alternatively, you can include the following instruction in the project's Intel® Quartus® Prime settings file (.qsf):
set_instance_assignment -name PRIORITY_SEU_AREA ON -to <partition name>
- Compile the design once all the settings are completed.
The Intel® Quartus® Prime software sets the internal scrubbing schedule of the priority sectors to "as fast as possible". The internal scrubbing schedule for other sectors follows the project's Minimum SEU interval global assignment.
With priority scrubbing enabled, the Quartus System Message window reports the summary of sectors for the priority scrubbing and non-priority scrubbing when you load your *.sof file in Quartus Programmer. This includes number of sectors, groups, and the minimum SEU interval.
Figure 6. Example of Quartus System Message with Priority and Regular SEU info
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