Intel® Stratix® 10 SEU Mitigation User Guide

ID 683602
Date 12/30/2022

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Document Table of Contents

2.1.1. Error Message Queue

The Intel® Stratix® 10 device error message queue stores the error messages when detecting an SEU error. Each error message contains information about the sector address, error type, and error location. The error message queue is capable of storing a maximum of eight different messages. A warning message appears if the error message queue has more than eight different messages. Click Read EMR to display and clear the error message queue.

You can retrieve the contents of the error message queue using the following tools:

  • Fault Injection Debugger tool
  • Advanced SEU Detection Intel® FPGA IP
Table 3.  Error Message Queue Description
Name Width Bit Description

Sector address

(Most significant 32-bit word in avst_seu_source_data signal

32 31:24 Reserved
23:16 Address of sector with error
15:4 Reserved
3:0 Number of errors detected in the sector minus one

Error location2

(Least significant 32-bit word in avst_seu_source_data signal)

32 31:29 Bit 31:29—Error type:
  • 001—single bit error
  • 010—uncorrectable double adjacent bits error
  • 011—uncorrectable multiple bits error
28 Correction Status:
  • 0=Not corrected
  • 1=Corrected
27:24 Reserved
23:12 Bit position within frame
11:0 Combined of Row and Frame index
Note: Intel® recommends that you turn on the Internal Scrubbing feature. If an error is detected in a sector, and you did not enable the Internal Scrubbing option, the SEU feature for that particular sector is turned off. Additionally, subsequent SEU occurrence in the same sector either correctable or uncorrectable error, is not detected.
2 For single bit error with internal scrubbing, the error location provides the error bit position. For multiple bits error or single bit error without internal scrubbing, bit [23:0] returns 0.