SDI IP Core User Guide

Download PDF
ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

3.1. Transmitter

The transmitter contains the following elements:
  • SD/HD-SDI transmitter scrambler
  • HD-SDI transmitter data formatter, which includes a CRC and LN insertion
  • Transceiver, plus control, and interface logic with multirate (dual or triple standard) SD/HD-SDI transmitter operation
  • Transmitter clock multiplexer (optional)

The transmitter performs the following functions:

  • HD-SDI LN insertion
  • HD-SDI CRC generation and insertion
  • Clock enable signal generation
  • Scrambling and non-return-zero inverted (NRZI) coding
  • Internal switching between two reference clock signals in the transmitter block. This feature is optional and only available for Arria II GZ and Stratix IV GX

The figure shows the top-level block diagram for the SDI transmitter.

Figure 4. SDI Transmitter Block Diagram


For HD-SDI, the transmitter accepts 20-bit parallel video data; for SD-SDI, 10-bit parallel data.

Table 7.  Bit Allocation for txdata for Supported Video StandardsThe table below lists the bit allocation for txdata.
txdata SD-SDI HD-SDI 3G-SDI Level A 3G-SDI Level B
[19:10] Unused Y Y Cb, Y, Cr, Y multiplex (link A)
[9:0] Cb, Y, Cr, Y multiplex C C Cb, Y, Cr, Y multiplex (link B)

For HD-SDI operation, the current video line number is inserted at the appropriate point in each line. A CRC is also calculated and inserted for the luma and chroma channels.

The parallel video data is scrambled and NRZI encoded according to the SDI specification.

The transceiver converts the encoded parallel data into the high-speed serial output (parallel-to-serial conversion).

HD-SDI LN Insertion

SMPTE292M section 5.4 defines the format of two words that are included in each HD-SDI video line to indicate the current line number. The HD-SDI LN insertion module takes the lower 11-bit tx_ln, formats and inserts it as two words in the output data. The HD-SDI LN insertion module accepts the current line number as an input.

The LN words (LN0 and LN1) overwrite the two words that follow the “XYZ” word of the EAV TRS sequence. The same value is included in the luma and chroma channels. For correct LN insertion, you must assert the tx_trs signal must be asserted for the first word of both EAV and SAV TRSs (refer to Figure 3–31 on page 3–47 and Figure 3–32 on page 3–48).

Note: If the system does not know the line number, you can implement logic to detect the output video format and then determine the current line. This function is outside the scope of this SDI MegaCore function.

HD-SDI CRC Generation and Insertion

SMPTE292M section 5.5 defines a CRC that is included in the chroma and luma channels for each HD-SDI video line. The HD-SDI CRC module generates, formats, and inserts the required CRC in the output data.

The HD-SDI CRC module identifies the words that you must include in the CRC calculation, and also determines where you must insert the words in the output data. The formatted CRC data words (YCR0 and YCR1 for the luma channel, CCR0 and CCR1 for the chroma channel) overwrite the two words that follow the line number words after the EAV. The module provides aseparate calculation for the luma and chroma channels.

The module calculates CRC for all words in the active digital line, starting with the first active word line and finishing with the final word of the line number (LN1). The initial value of the CRC is set to zero, then the polynomial generator equation CRC(X) = X18 + X5 + X4 + 1 is applied.

The HD-SDI CRC module implements the CRC calculation by iteratively applying the polynomial generator equation to each bit of the output data, processing the LSB first.

For correct CRC generation and insertion, the tx_trs signal must be asserted for the first word of both EAV and SAV TRS (refer to Figure 3–31 on page 3–47 and Figure 3–32 on page 3–48).

Scrambling and NRZI Coding

SMPTE292M section 5 and SMPTE292M section 7 define a common channel coding that is used for both SDI and HD-SDI. This channel coding consists of a scrambling function (G1(X) = X9 + X4 + 1) followed by NRZI encoding (G2(X) = X + 1). The scrambling module implements this channel coding. You can configure the module to process either 10-bit or 20-bit parallel data.

The scrambling module implements the channel coding by iteratively applying the scrambling and NRZI encoding algorithm to each bit of the output data, processing the LSB first. Figure C.1 of SMPTE259M shows how the algorithm is implemented.

Transceiver Clock

The tx_serial_refclk1 is an optional port that is enabled when you turn on the Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration in the parameter editor.

Figure 5. Transmitter Clocking Scheme

This table shows the clocking scheme for the transmitter.

Level Two Title