SDI IP Core User Guide

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ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

3.3.1. Transmitter Clocks

The transmitter requires two clocks: a parallel video clock (tx_pclk) and a transmitter reference clock (tx_serial_refclk).
The parallel video clock samples and processes the following parallel video input:
  • SD-SDI—27 MHz
  • HD-SDI—74.25 or 74.175 MHz
  • 3G-SDI—148.5 or 148.35 MHz
The transceiver uses the transmitter reference clock to generate the high-speed serial output. The transceiver is configured for 20-bit operation, so the reference clock is 1/20th of the serial data rate.
Note: For SD-SDI, because of the oversampling implementation, the serial data rate is five times the SDI bit rate (for example, 1,350 Mbps); for the triple-standard SDI, the oversampling rate is 11.

For SD-SDI operation, the transmitter reference clock can be derived from pclk by using one of the transceiver PLLs. The PLL can multiply the 27-MHz pclk signal by 5/2.

For all other standards, use an external multiplexer to select between the alternative reference clocks.
Table 11.  Transmitter Clock FrequencyThis table lists the frequencies of the transmitter clock, tx_serial_refclk, for Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix IV, and Stratix V devices.
Video Standard Clock Frequency (MHz)
SD-SDI 67.5
HD-SDI (including dual link) 74.175 or 74.25
HD-SDI with two times oversample 148.35 or 148.5
Dual standard 67.5, 74.175 or 74.25
Tripe standare 148.35 or 148.5
3G-SDI 148.35 or 148.5
Note: You must multiplex the tx_serial_refclk signal externally for all the video standards, except for SD-SDI,. If you enable the additional input reference clock port for the serial reference clock, the external multiplier is no longer required.
The following figures show the transmitter clocks for Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix IV, and Stratix V devices.
Figure 10. Transmitter Clock for SD-SDI
Figure 11. Transmitter Clock for HD-SDIThe frequency supported for this clock can be 74.175 or 74.25 MHz, to support 1.4835 or 1.485 Gbps HD-SDI respectively.
Figure 12. Transmitter Clock for Dual StandardThe multiplexer must be in the device.
Figure 13. Transmitter Clock for 3G-SDI and Triple StandardThe frequency supported for this clock can be either 148.35 or 148.5 MHz, to support 2.967 or 2.970 Gbps HD-SDI respectively
Figure 14. Transmitter Clock for 3G-SDI and Triple Standard with Additional Reference Clock PortYou can source both 148.5 MHz and 148.35 MHz clocks together if the additional clock port is enabled.
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