SDI IP Core User Guide

ID 683587
Date 8/20/2020
Public
Document Table of Contents

6. Document Revision History for the SDI IP Core User Guide

Table 20.  Document Revision History
Document Version Intel® Quartus® Prime Version Changes
2020.08.20 19.1
  • Rebranded as Intel.
  • Added notification that Intel has discontinued support for this IP core. You may continue to use this IP without support. However, Intel recommends that you use the SDI II Intel® FPGA IP for the latest features and continued support.
  • Removed information about the following devices:
    • Arria GX
    • Cyclone, Cyclone II, and Cyclone III
    • HardCopy III and HardCopy IV
    • Stratix, Stratix II, and Stratix III
    Intel no longer supports these devices.
  • Removed the SDI Audio IP Cores chapter from the user guide. Refer to the SDI Audio Intel® FPGA IP User Guide for SDI audio information.

Date

Version

Changes

February 2013 12.1
  • Updated Table 1–2, Table 1–4, Table 1–5, and Table 1–7 for version 12.1 release.
  • Updated information on duplex setting in Table 3–10.
  • Updated information on rx_video_format signal in Table 3–12.
  • Added a note in Table 3–13 to include information about Arria V and Stratix V devices.
  • Added Table 3–14—transceiver PHY management clock and reset signals.
  • Updated information on rx_status signal in Table 3–18.
  • Added data width information for SDI_RECONFIG_TOGXB and SDI_RECONFIG_FROMGXB signals in Table 3–19.
  • Updated the Starting channel number parameter description in Table 3–21.
  • Added reset sequence information and timing diagram in Figure 3–25.
November 2011 12.0
  • Added information about Arria V and Stratix V devices.
  • Updated Table 1–2, Table 1–5, Table 1–6, and Table 1–7 for version 11.1 release.
  • Updated Parameterizing section to include additional steps to turn on the Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration option.
  • Updated Transmitter Clocks and Transceiver—Arria GX, Arria II GX, Arria V, Cyclone IV GX, Cyclone V, Stratix II GX, Stratix IV GX, and Stratix V Devices section and, Table 3–7, Table 3–9, Figure 3–3, and Figure 3–8, to include information about the optional serial reference clock feature.
  • Updated Table 3–21 with Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration parameter.
  • Updated information in the Transceiver Dynamic Reconfiguration for Dual Standard and Triple Standard Receivers section.
  • Updated Table 4–1, Table 4–4, and Table 4–14 to include information about asynchronous and synchcronous modes.
July 2011 11.1
  • Added information about accessing transceiver.
  • Updated Table 3–12 with new signals, refclk_rate and rx_video_format.
  • Updated the high-level block diagram of design example for the SDI Audio IP Core to include AES input and output modules.
  • Updated the SDI Audio IP Core register maps.
December 2010 11.0
  • Added two new GUI parameters for SDI MegaCore function: Enable Spread Spectrum feature and Tolerance to consecutive missed EAV.
  • Added a chapter on the SDI Audio IP Cores: SDI Audio Embed, Audio Extract, Clocked Audio Input, and Clocked Audio Output MegaCore functions.
July 2010 10.1
  • Added information for Cyclone IV devices.
  • Added a section on transceiver dynamic reconfiguration with PLL reconfiguration mode - Cyclone IV GX.
  • Added transceiver dynamic reconfiguration signals for PLL reconfiguration in Table 3–18.
  • Updated Figure 3–29 and Figure 3–30 to include tx_ln signal behavior.
November 2009 10.0
  • Added Cyclone III LS and Cyclone IV support.
  • Added a section on Specify Constraints.
  • Updated information on rst_rx and rst_tx signals in Table 3–15.
  • Added block diagram for input and output interface signals flow.
  • Added top-level block diagram for transmitter and receiver.
May 2009 9.1
  • Added a section on Reset Requirement During Reconfiguration.
  • Updated information on txdata, tx_ln, crc_error_y, crc_error_c, rx_AP, rxdata, rx_data_valid_out, rx_F, rx_H, rx_ln, and rx_V signals in Table 3–15.
  • Updated information on rx_anc_data, rx_anc_error, rx_anc_valid, and rx_status signals in Table 3–17.
March 2009 9.0
  • Added Arria II GX support.
  • Added a section on RP168.
  • Updated information on video formats.
  • Removed tx_data_valid_a_bn signal.
November 2008 9.0
  • Added a section on Locking Algorithm.
  • Added new signals and updated existing signal descriptions.
  • Updated Appendix A: Constraints.
May 2008 8.1
  • Added Stratix IV support.
  • Improved receiver lock algorithm.
  • Updated 425MB support.
October 2007 8.0
  • Updated device support.
  • Updated standards support—3G-SDI now supports SMPTE425M-B 2006 3Gb/s Signal/Data Serial Interface – Source Image Format Mapping.
  • Changed rx_std signal description.
  • Added tx_data_valid_a_bn signal.
May 2007 7.2
  • Updated device support.
  • Added dual and triple standard information.
  • Added transceiver dynamic reconfiguration information.
December 2006 7.0 Added support for Cyclone III devices.
December 2006 6.1 Updated for new MegaWizard Plug-In Manager.