SDI IP Core User Guide

ID 683587
Date 8/20/2020
Document Table of Contents

C.1. Loopback FIFO Buffer

For more efficient transmission, place a FIFO or buffer between the receiver clock domain logic and the transmit clock domain logic.
The decoded receiver data connects to the transmitter input through a FIFO buffer. When the receiver is locked, the logic writes the receiver data to the FIFO buffer. When the FIFO is half full, the transmitter starts reading, encoding and transmitting the data.
Figure 39. Receive and Retransmit Clock SchemeThe figure shows the clocking scheme of the received and retransmitted data.