SDI IP Core User Guide

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ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

4.3. SDI Status Signals

Signal

Width

Direction

Description

rx_anc_data [(20N–1):0] Output
Received ancillary data.
  • SD-SDI: bits 19:10 unused; bits 9:0 Cb, Y, Cr, Y multiplex
  • HD-SDI: bits 19:10 Y; bits 9:0 C
  • Dual link: bits 39:30 Y (link B); bits 29:20 C (link B); bits 19:10 Y (link A); bits 9:0 C (link A)
  • 3G-SDI Level A: bits 19:10 Y; bits 9:0 C
  • 3G-SDI Level B: bits 19:10 Cb, Y, Cr, Y multiplex (link A); bits 9:0 Cb, Y, Cr, Y multiplex (link B)
rx_anc_error [3:0] Output
Ancillary data or checksum error.
  • SD-SDI: bits 3:1 unused; bits 0 rx_anc_error
  • HD-SDI: bits 3:2 unused; bit 1 Y; bit 0 C
  • Dual link: bit 3 Y (link B); bit 2 C (link B); bit 1 Y (link A); bit 0 C (link A)
  • 3G-SDI Level A: bits 3:2 unused; bit 1 Y; bit 0 C
  • 3G-SDI Level B: bit 3 Y (link A); bit 2 C (link A); bit 1 Y (link B); bit 0 C (link B)
rx_anc_valid [3:0] Output
Ancillary data valid. Asserted to accompany data ID (DID), secondary data ID/data block number (SDID/DBN), data count (DC), and user data words (UDW) on rx_anc_data.
  • SD-SDI: bits 3:1 unused; bits 0 rx_anc_valid
  • HD-SDI: bits 3:2 unused; bit 1 Y; bit 0 C
  • Dual link: bit 3 Y (link B); bit 2 C (link B); bit 1 Y (link A); bit 0 C (link A)
  • 3G-SDI Level A: bits 3:2 unused; bit 1 Y; bit 0 C
  • 3G-SDI Level B: bit 3 Y (link A); bit 2 C (link A); bit 1 Y (link B); bit 0 C (link B)
rx_status [10:0] Output

This signal is active low for the transceiver-based device families.

Receiver status:
  • rx_status[10] dual link ports aligned
  • rx_status[9] link B frame locked
  • rx_status[8] link B TRS locked (six consecutive TRSs with same timing)
  • rx_status[7] link B alignment locked (a TRS has been spotted and word alignment performed)
  • rx_status[6] link B receiver in reset
  • rx_status[5] link B transceiver PLL locked
  • rx_status[4] link A frame locked
  • rx_status[3] link A TRS locked (six consecutive TRSs with same timing
  • rx_status[2] link A alignment locked (a TRS has been spotted and word alignment performed)
  • rx_status[1] link A receiver in reset
  • rx_status[0] link A transceiver PLL locked

For non HD-SDI dual link versions, only bits [4:0] are active.

For transceiver only receiver block in HD-SDI dual link versions, only bits [6:5] and [1:0] are active.

This signal indicates lock of the PLL when the transceiver is training from a refclk source. This signal may oscillate when the transceiver is correctly locked to the incoming data in HD-SDI or 3G-SDI modes. In SD-SDI modes, maintain this signal at PLL locked at all times.

For rx_status[3] and rx_status[8], the TRS spacing is not required to meet a particular SMPTE standard, but it must be consistent over time for this signal to remain active.

tx_status [(N– 1):0] Output

This signal is active low for the transceiver-based device families.

Transmitter status, which indicates the transmitter PLL has locked to the tx_serial_refclk signal.

The following figures show the behavior of the rx_anc_data signal.

Figure 33. Behavior of rx_anc_data/valid/error Signals—425MA/HD
Figure 34. Behavior of rx_anc_data/valid/error Signals—425MB
Figure 35. Behavior of rx_anc_data/valid/error Signals Without Error—SD
Figure 36. Behavior of rx_anc_data/valid/error Signals With Error—SD
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