4.1. SDI Clock Signals
| Signal |
Direction |
Description |
|---|---|---|
| gxb4_cal_clk | Input | Calibration clock for Arria II GX, Arria V, Cyclone IV GX, and Stratix IV transceivers only. |
| rx_sd_oversample_clk_in | Input | 67.5-MHz oversample clock input. SD-SDI only. |
| rx_serial_refclk | Input | Transceiver training clock for HD-SDI, dual standard and triple standard.
Note: You must tie the tx_serial_refclk and rx_serial_refclk signals together if you generate an SDI duplex using the Stratix V or Arria V devices.
|
| rx_serial_refclk1 | Input | Secondary transceiver training clock. Clock frequency of 74.175 MHz for HD-SDI, or clock frequency of 148.35 MHz for 3G-SDI, dual standard and triple standard. Available only when you use a Cyclone IV GX device. |
| rx_coreclk | Input | Receiver controller clock input. For Cyclone IV GX devices only. The frequency of this clock must be the same as rx_serial_refclk. Because of hardware constraint, the transceiver PLL and core logic cannot share the same clock input pin if they use transceiver PLL6 and PLL7. |
| refclk_rate | Input | This signal is related to the rx_video_format signal. Detects the received video standard. Set input to 0 for a 148.35-MHz receiver serial reference clock. Set input to 1 for 148.5-MHz RX serial reference clock.
Note: For Cyclone IV GX devices, set the refclk_rate according to the rx_coreclk frequency.
|
| gxb_tx_clkout | Output | Transmitter clock out of transceiver. This clock is the output of the voltage-controlled oscillator (VCO) and is used as a parallel clock for the transmitter. It connects internally to the tx_clkout signal of the ALTGX or ALT2GXB megafunction. |
| rx_clk | Output | Transceiver CDR clock. |
| rx_sd_oversample_clk_out | Output | 67.5-MHz oversample clock output for cascading MegaCore functions. SD-SDI only. |
| rx_video_format | Output | This signal is related to the refclk_rate signal. Indicates the format for the received video. The rx_video_format value is valid after the frame locked signal is asserted. |
| Signal |
Direction |
Description |
|---|---|---|
| tx_pclk | Input | Transmitter parallel clock input.
|
| tx_serial_refclk | Input | Transceiver reference clock input; with low jitter.
Note: You must tie the tx_serial_refclk and rx_serial_refclk signals together if you generate an SDI duplex using the Stratix V or Arria V devices.
|
| tx_serial_refclk1 | Input | Optional port for transceiver reference clock input; with low jitter. Similar to tx_serial_refclk.
Note: Only available for Arria II, and Stratix IV GX devices.
|
| Signal |
Direction |
Description |
|---|---|---|
| phy_mgmt_clk | Input | Avalon-MM clock input for the transceiver PHY management interface. Use the same clock for the PHY management interface and transceiver reconfiguration. The frequency range is 100-125 MHz to meet the specification of the transceiver reconfiguration clock. |
| phy_mgmt_clk_reset | Input | Reset signal for the transceiver PHY management interface. This signal is active high and level sensitive. This signal can be tied to the same reset port as tx_rst or rx_rst signal in simplex mode. In duplex mode, this reset signal acts as a global reset for both the transmitter and receiver. If you require a different reset for the transmitter and receiver, separate this signal from the tx_rst and rx_rst signal. |
| rx_sd_refclk_337 | Input | Soft transceiver 337.5-MHz sampling clock. |
| rx_sd_refclk_337_90deg | Input | Soft transceiver 337.5-MHz sampling clock with 90° phase shift. |
| rx_sd_refclk_135 | Input | Soft transceiver 135-MHz parallel clock for receiver. |
| rx_sd_refclk_270 | Input | Soft transceiver 270-MHz parallel clock for transmitter. |