SDI IP Core User Guide

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ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

3.3.2. Receiver Clocks

The transceiver requires a receiver reference clock, rx_serial_refclk. This clock trains the receiver PLL in the transceiver.
  • For SD-SDI operation, the clock must be nominally 1/4th of the serial data rate (for example, 67.5 MHz). The clock does not have to be frequency locked to the data.
  • For HD-SDI operation, the clock must be nominally 1/20th of the serial data rate. The clock does not have to be frequency locked to the data, because the design only uses it for the training of the receiver PLL.
  • For dual or triple standard operation, the receiver reference clock must be 148.5 MHz. In this mode, the transceiver oversamples the SD-SDI signals by a factor of 11.

All receiver interfaces share a common receiver reference clock.

Table 12.  Receiver Clock FrequencyThis table shows the frequencies of the receiver clock, rx_serial_refclk.
Video Standard Clock Frequency (MHz)
SD-SDI 67.5
HD-SDI 74.175 or 74.25
Dual or triple standard 148.35 or 148.56
3G-SDI 148.35 or 148.5
Figure 15. Receiver Clocks for Different Standards
6 For correct SD-SDI operation, you must use only 148.5 MHz
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