SDI IP Core User Guide

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ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

4.2. SDI Interface Signals

Signal

Width

Direction

Description

enable_crc [(N–1):0] Input Enables CRC insertion for HD-SDI and 3G-SDI.
enable_sd_search [1:0] Input Enables search for SD-SDI signal in dual or triple standard mode.
enable_hd_search [1:0] Input Enables search for HD-SDI signal in dual or triple standard mode.
enable_3g_search [1:0] Input Enables search for 3G-SDI signal in triple standard mode.
enable_ln [(N– 1):0] Input Enables line number (LN) insertion for HD-SDI and 3G-SDI.
en_sync_switch [1:0] Input Enables aligner and format blocks to realign immediately so that the downstream is completely non-disruptive.
rst_rx [1:0] Input Reset signal, which holds the receiver in reset.

For Cyclone IV GX devices, this signal must be synchronous to the rx_coreclock clock domain for the receiver. Issues a reset to the SDI IP core after power-up to ensure reliable operation.

For HD-SDI dual link receiver, assert this signal when both link A and link B are ready for the first time.

rst_tx [1:0] Input Reset signal, which holds the transmitter in reset. The reset synchronization for the transmitter is handled within the SDI IP core.
Note: The video mode (tx_std) and clocks must be set up and stable before device bring-up or core reset.

Issues a reset to the SDI IP core after power-up to ensure reliable operation.

rx_serial_refclk_clkswitch [1:0] Input Reference clock switching.

Available only when you use a Cyclone IV GX device.

Toggle between rx_serial_refclk and rx_serial_refclk1 at every positive edge triggered.

rx_protocol_clk [(N–1):0] Input External clock for protocol data.
rx_protocol_hd_sdn [(N–1):0] Input Selection of HD-SDI or SD-SDI processing for dual or triple standard protocol block.

This signal only appears on dual or triple standard protocol blocks and indicates 3G-SDI(1), HD-SDI(1) or SD-SDI(0) data on the rx_protocol_in signal. You must connect this signal to the rx_std_flag_hd_sdn output of the transceiver block in a split protocol/transceiver design.

rx_protocol_in [(20N–1):0] Input External data input for protocol only mode.
rx_protocol_locked [(N–1):0] Input Input to transceiver control logic. When active, this signal indicates to the transceiver control logic that the protocol blocks are locked, to stop the transceiver search algorithm at the current rate.
rx_protocol_rst [(N–1):0] Input Reset for the protocol block. This signal resets the protocol blocks.

You can connect this signal to the rx_status[1] pin (sdi_reset) in a split transceiver/protocol design.

rx_protocol_valid [(N–1):0] Input External data valid in for protocol only mode.
rx_protocol_rate [1:0] Input Input to the protocol block. This signal indicates the received video standard to the protocol block.

However, this signal does not distinguish between 3G-SDI Level A and 3G-SDI Level B streams. The aligner block in the protocol block distinguishes the 3G-SDI Level A and 3G-SDI Level B streams. You must connect this signal to the rx_std port of the transceiver block in a split transceiver/protocol design.

rx_xcvr_trs_lock [(N–1):0] Input Input to transceiver control logic. You must connect this signal to the rx_status[3] pin (trs_locked) of the protocol only receiver block.
sdi_rx [(N–1):0] Input Serial input.
txdata [(20N–1):0] Input
User-supplied transmitter parallel data valid. SD-SDI uses 9:0; HD-SDI uses 20N – 1:0.
  • SD-SDI = bits 19:10 unused; bits 9:0 Cb, Y, Cr, Y multiplex
  • HD-SDI = bits 19:10 Y; bits 9:0 C
  • Dual Link = bits 39:30 Y link B; bits 29:20 C link B; bits 19:10 Y link A, bits 9:0 C link A
  • 3G-SDI Level A = bits 19:10 Y; bits 9:0 C
  • 3G-SDI Level B = bits 19:10 Cb, Y, Cr, Y multiplex (link A); bits 9:0 Cb, Y, Cr, Y multiplex (link B)
tx_ln [21:0] Input
Transmitter line number.
  • HD-SDI = bits 21:11 11’d0; bits 10:0 LN
  • Dual Link = bits 21:11 LN link B; bits 10:0 LN link A
  • 3G-SDI Level A = bits 21:11 11’d0; bits 10:0 LN
  • 3G-SDI Level B = bits 21:11 LN link A; bits 10:0 LN link B
tx_trs [(N–1):0] Input Transmitter TRS input. For use in HD-SDI LN and CRC insertion.

Assert on first word of both EAV and SAV TRSs.

tx_std [1:0]
Transmitter standard.
  • SD-SDI = 00
  • HD-SDI = 01
  • 3G-SDI Level A = 11
  • 3G-SDI Level B = 10
Note: This signal must be set up and stable prior to device bring-up or core reset.
trs_loose_lock [(N–1):0] Output TRS locking signal for protocol only receiver mode. You can connect this signal to the rx_protocol_locked pin of the transceiver only receiver block.
crc_error_y [1:0] Output
CRC error on luma channel.
  • HD-SDI: bit 1 unused; bit 0 crc_error_y
  • Dual link: bit 1 link B crc_error_y; bit 0 link A crc_error_y
  • 3G-SDI Level A: bit 1 unused; bit 0 crc_error_y
  • 3G-SDI Level B: bit 1 link A crc_error_y; bit 0 link B crc_error_y
crc_error_c [1:0] Output
CRC error on chroma channel.
  • HD-SDI: bit 1 unused; bit 0 crc_error_c
  • Dual link: bit 1 link B crc_error_c; bit 0 link A crc_error_c
  • 3G-SDI Level A: bit 1 unused; bit 0 crc_error_c
  • 3G-SDI Level B: bit 1 link A crc_error_c; bit 0 link B crc_error_c
rx_AP [1:0] Output
This is an active picture interval timing signal. The receiver asserts this signal when the active picture interval is active.
  • SD-SDI/HD-SDI: bit 1 unused; bit 0 rx_ap
  • Dual link: bit 1 link B unused; bit 0 link A rx_ap
  • 3G-SDI Level A: bit 1 unused; bit 0 rx_ap
  • 3G-SDI Level B: bit 1 link A rx_ap; bit 0 link B rx_ap
rxdata [(20N–1):0] Output
Receiver parallel data. SD-SDI uses 9:0; HD-SDI uses 20N–1:0.

  • SD-SDI bits 19:10 unused; bits 9:0 Cb, Y, Cr, Y multiplex

  • HD-SDI bits 19:10 Y; bits 9:0 C
  • Dual link: bits 39:30 Y link B; bits 29:20 C link B; bits 19:10 Y link A, bits 9:0 C link A
  • 3G-SDI Level A: bits 19:10 Y; bits 9:0 C
  • 3G-SDI Level B: bits 19:10 Cb, Y, Cr, Y multiplex (link A); bits 9:0 Cb, Y, Cr, Y multiplex (link B)
rx_data_valid_out [1:0] Output

Data valid from the oversampling logic. Asserted to indicate current data on rxdata is valid.

Bit 0 of this bus indicates valid data on rxdata. When receiving SMPTE 425M-B signals in 3G-SDI or triple standard, bit 1 indicates that data on rxdata is from virtual link A; bit 0 indicates the data is from virtual link B.

rx_F [1:0] Output
This is a field bit timing signal. This signal indicates which video field is currently active. For interlaced frame, 0 means first field (F0) while 1 means second field (F1). For progressive frame, the value is always 0.
  • SD-SDI/HD-SDI: bit 1 unused; bit 0 rx_f
  • Dual link: bit 1 unused; bit 0 rx_f
  • 3G-SDI Level A: bit 1:0 unused
  • 3G-SDI Level B: bit 1:0 unused
rx_H [1:0] Output
This is a horizontal blanking interval timing signal. The receiver asserts this signal when the horizontal blanking interval is active.
  • SD-SDI/HD-SDI: bit 1 unused; bit 0 rx_h
  • Dual link: bit 1 unused; bit 0 rx_h
  • 3G-SDI Level A: bit 1 unused; bit 0 rx_h
  • 3G-SDI Level B: bit 1 link A rx_h; bit 0 link B rx_h
rx_ln [21:0] Output
Receiver line number.
  • HD-SDI = bits 21:11 unused; bits 10:0 LN
  • Dual Link = bits 21:11 unused; bits 10:0 LN
  • 3G-SDI Level A = bits 21:11 unused; bits 10:0 LN
  • 3G-SDI Level B = bits 21:11 LN link A; bits 10:0 LN link B
rx_std_flag_hd_sdn 1 Output Indicates received standard for dual or triple standard only.

HD-SDI = 1; SD-SDI = 0.

rx_V [1:0] Output
This is a vertical blanking interval timing signal. The receiver asserts this signal when the vertical blanking interval is active.
  • SD-SDI/HD-SDI: bit 1 unused; bit 0 rx_v
  • Dual link: bit 1 unused; bit 0 rx_v
  • 3G-SDI Level A: bit 1 unused; bit 0 rx_v
  • 3G-SDI Level B: bit 1 link A rx_v; bit 0 link B rx_v
rx_xyz 1 Output Receiver output that indicates current word is XYZ word.
xyz_valid 1 Output Receiver output that indicates current TRS format is legal (XYZ word is correct).
rx_eav 1 Output Receiver output that indicates current TRS is EAV.
rx_trs 1 Output Receiver output that indicates current word is TRS. This signal is asserted at the first word of 3FF 000 000 TRS.
sdi_tx [(N–1):0] Output Serial output.
tx_protocol_out [(20N–1):0] Output Data out (protocol only mode).

The following figures illustrate the input and output interface signals for SDI triple standard instances.

Figure 21. Interface Signals for SDI Triple Standard Receiver
Figure 22. Interface Signals for SDI Triple Standard Transmitter
Figure 23. Interface Signals for SDI Triple Standard Duplex Instance

The following figures show the behavior of certain SDI interface signals.

Figure 24. Power-up Reset for the Receiver
Figure 25. Power-up Reset for the Transmitter rst_tx_sync is an internally synchronized reset for the transmit circuits.
Figure 26. Behavior of tx_std, tx_trs, and tx_ln Signals—425MA
Figure 27. Behavior of tx_std, tx_trs, and tx_ln Signals—425MB
Figure 28. Behavior of crc_error_y and crc_error_c Signals

When a CRC error occurs, the crc_error_y or crc_error_c signal goes high until the next line. For HD, Dual Link, and 3G Level A, only crc_error_y[0] and crc_error_c[0] signals are used. For 3G Level B, crc_error_y[0] and crc_error_c[0] signals are used for link B, and crc_error_y[1] and crc_error_c[1] signals are used for link A.

Figure 29. Behavior of rx_data_valid Signal—425MA
Figure 30. Behavior of rx_data_valid Signal—425MB
Figure 31. Behavior of rx_trs, rx_xyz, xyz_valid and rx_eav Signals—425MA
Figure 32. Behavior of rx_trs, rx_xyz, xyz_valid and rx_eav Signals—425MB
Level Two Title